AMC1336 datasheet(9/31 Pages) TI1

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CLKIN

DOUT

Bitream not valid

(analog settling)

tISTART

DVDD

...

Valid bitstream

AVDD

Test Pattern

tASTART

CLKIN

DOUT

tCLKIN

tHIGH

tLOW

tr / tf

AMC1336

www.ti.com

SBAS951 – AUGUST 2019

Product Folder Links: AMC1336

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(1)

The duty cycle of DOUT equals the clock duty cycle of the applied CLKIN signal.

6.10 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fCLKIN

CLKIN clock frequency

MHz

DutyCycl

CLKIN duty cycle(1)

40%

50%

60%

tH1

DOUT hold time after rising edge

of CLKIN

CLOAD = 15 pF

3.5

tD1

Rising edge of CLKIN to DOUT

valid delay

CLOAD = 15 pF

DOUT rise time

10% to 90%, 2.7 V

≤ DVDD ≤ 3.6 V, CLOAD = 15 pF

0.8

3.5

10% to 90%, 4.5 V

≤ DVDD ≤ 5.5 V, CLOAD = 15 pF

1.8

3.9

DOUT fall time

10% to 90%, 2.7 V

≤ DVDD ≤ 3.6 V, CLOAD = 15 pF

0.8

3.5

10% to 90%, 4.5 V

≤ DVDD ≤ 5.5 V, CLOAD = 15 pF

1.8

3.9

tASTART

Analog startup time

AVDD step to 3.0 V; 0.1%-settling, clock applied

0.5

tISTART

Interface startup time

DVDD step to 2.7 V; 0.1%-settling, clock applied

CLKIN

cycles

Figure 1. Digital Interface Timing

Figure 2. Device Start-Up Timing

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