82801DB datasheet(18/587 Pages) INTEL

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Intel® 82801DB ICH4 Datasheet

Figures

System Configuration ...................................................................................... 4

2-1

Intel® ICH4 Interface Signals Block Diagram................................................. 38

2-2

Example External RTC Circuit ....................................................................... 54

2-3

Example V5REF Sequencing Circuit ............................................................. 55

4-1

Conceptual System Clock Diagram ............................................................... 66

5-1

Primary Device Status Register Error Reporting Logic.................................. 69

5-2

Secondary Status Register Error Reporting Logic ......................................... 69

5-3

NMI# Generation Logic.................................................................................. 70

5-4

Integrated LAN Controller Block Diagram...................................................... 73

5-5

64-Word EEPROM Read Instruction Waveform ............................................ 83

5-6

LPC Interface Diagram .................................................................................. 86

5-7

Typical Timing for LFRAME# ......................................................................... 90

5-8

Abort Mechanism ........................................................................................... 90

5-9

Intel® ICH4 DMA Controller ........................................................................... 92

5-10

DMA Serial Channel Passing Protocol .......................................................... 96

5-11

DMA Request Assertion Through LDRQ# ..................................................... 99

5-12

Coprocessor Error Timing Diagram ............................................................. 131

5-13

Signal Strapping .......................................................................................... 134

5-14

Physical Region Descriptor Table Entry ...................................................... 165

5-15

Transfer Descriptor ...................................................................................... 173

5-16

Example Queue Conditions ......................................................................... 181

5-17

USB Data Encoding..................................................................................... 184

5-18

USB Legacy Keyboard Enable and Status Paths........................................ 193

5-19

Intel® ICH4 USB Port Connections.............................................................. 202

5-20

Intel® ICH4 Based Audio Codec ’97 Specification, Revision 2.3 ................. 229

5-21

AC ’97 2.3 Controller-Codec Connection..................................................... 230

5-22

AC-Link Protocol.......................................................................................... 231

5-23

AC-Link Powerdown Timing ........................................................................ 238

5-24

SDIN Wake Signaling .................................................................................. 239

16-1

Intel® ICH4 Ballout (Topview—Left Side) .................................................... 512

16-2

Intel® ICH4 Ballout (Topview—Right Side).................................................. 513

17-1

Clock Timing ................................................................................................ 539

17-2

Valid Delay from Rising Clock Edge ............................................................ 539

17-3

Setup and Hold Times ................................................................................. 539

17-4

Float Delay................................................................................................... 540

17-5

Pulse Width.................................................................................................. 540

17-6

Output Enable Delay.................................................................................... 540

17-7

IDE PIO Mode.............................................................................................. 541

17-8

IDE Multiword DMA ..................................................................................... 541

17-9

Ultra ATA Mode (Drive Initiating a Burst Read) ........................................... 542

17-10

Ultra ATA Mode (Sustained Burst) .............................................................. 542

17-11

Ultra ATA Mode (Pausing a DMA Burst) ..................................................... 543

17-12

Ultra ATA Mode (Terminating a DMA Burst) ............................................... 543

17-13

USB Rise and Fall Times............................................................................. 543

17-14

USB Jitter..................................................................................................... 544

17-15

USB EOP Width........................................................................................... 544

17-16

SMBus Transaction ..................................................................................... 544

17-17

SMBus Timeout ........................................................................................... 545

17-18

Power Sequencing and Reset Signal Timings............................................. 545

82801DB Datasheet(PDF) 18 Page - Intel Corporation

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