CBM708 datasheet(9/18 Pages) COREBAI

9 / 18 page

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CBM705/CBM706/CBM707/CBM708

OPERATION INSTRUCTION

CIRCUIT INFORMATION

POWER FAIL RESET OUTPUT

RESET is an active low output that provides a reset signal to the microprocessor whenever

the VCC input is below the reset threshold. An internal timer holds RESET low for 200 ms after

the voltage on VCC rises above the threshold. This functions as a power-on reset signal for the

microprocessor. It allows time for both the power supply and the microprocessor to stabilize

after power-up. The RESET output is guaranteed to remain valid (low) with VCC as low as 1V. This

ensures that the microprocessor is held in a stable shutdown condition as the power supply

voltage ramps up.

In addition to RESET, an active high RESET output is also available on the CBM707/CBM708.

This is the complement of RESET and is useful for processors requiring an active high reset

signal.

MANUAL RESET

The manual reset input (MR) allows other reset sources, such as a manual reset switch, to

generate a processor reset. The input is effectively debounced by the timeout period (200 ms

typically). The MR input is TTL-/CMOS-compatible, so it can also be driven by any logic reset

output.

Figure 13. RESET, MR, and WDO Timing

CBM708 Datasheet(PDF) 9 Page - COREBAI Microelectronics (Beijing) Co., Ltd.