| Electronic Components Datasheet Search |
|
FC9911 Datasheet(PDF) 11 Page - First Silicon Co., Ltd |
|
|
|||||||||||||||||||||||||||||
FC9911 Datasheet(HTML) 11 Page - First Silicon Co., Ltd |
|
11 / 13 page ![]() FET (Q 1) during an output short circuit condition will not remove the fault (Q 1 is not in the path of the fault current). The disconnect switch will help to disconnect the shorted load from the input. Over Voltage Protection Over voltage protection is achieved by connecting the output voltage to the OVP pin through a resistive divider. The voltage . V 5 2 . 1 l a n r e t n i e h t o t d e r a p m o c y lt n a t s n o c s i n i p P V O e h t t a When the voltage at this pin exceeds 1.25V, the IC is turned off and FAULT goes low. Output Short Circuit Protection The output short circuit condition is indicated by FAULT. At startup, a monoshot circuit, (triggered by the POR circuit), resets an internal flip-flop, which causes FAULT to go high, and remains high during normal operation. This also allows the GATE drive to function normally. The steady state current is reflected in the reference voltage connected to the transconductance amplifier. The instantaneous output current is sensed from the FDBK terminal of the amplifier. The short circuit threshold current is internally set to 200% of the steady state current. During short circuit condition, when the current exceeds the internally set threshold, the SR flip-flop is set and FAULT goes low. At the same time, the GATE driver of the power FET is inhibited, providing a latching protection. The system can be reset by cycling the input voltage to the IC. Note: The short circuit FET should be connected before the current sense resistor as reversing R S and Q2 will affect the accuracy of the output current (due to the additional voltage drop across Q 2 which will be sensed). Synchronization The SYNC pin is an input/output (I/O) port to a fault tolerant peer-to-peer and/or master clock synchronization circuit. For synchronization, the SYNC pins of multiple FC9911 based converters can be connected together, and may also . k c o l c r e t s a m a f o t u p t u o n i a r d n e p o e h t o t d e t c e n n o c e b When connected in this manner, the oscillators will lock to the device with the highest operating frequency. When synchronizing multiple ICs, it is recommended that the same timing resistor, corresponding to the switching frequency, be used in all the FC9911 circuits. On rare occasions, given the length of the connecting lines for the SYNC pins, a resistor between SYNC and GND may be required to damp any ringing due to parasitic capacitances. It is recommended that the resistor chosen be greater than 300kΩ. When synchronized in this manner, a permanent HIGH or LOW condition on the SYNC pin will result in a loss of synchronization, but the FC9911 based converters will continue to operate at their individually set operating frequency. Since loss of synchronization will not result in total system failure, the SYNC pin is considered fault tolerant. Note: The FC9911 is designed to SYNC up to four ICs at a time without the use of an external buffer. To SYNC more than four ICs, it is recommended that a buffered external clock be used. Internal 1MHz Transconductance Amplifier FC9911 includes a built in 1MHz transconductance amplifier, with tri-state output, which can be used to close the feedback loop. The output current sense signal is connected to the FDBK pin and the current reference is connected to the IREF pin. The output of the opamp is controlled by the signal applied to the PWMD pin. When PWMD is high, the output of the opamp is connected to the COMP pin. When PWMD is low, the output is left open. This enables the integrating capacitor to hold the charge when the PWMD signal has turned off the GATE drive. When the IC is enabled, the voltage on the integrating capacitor will force the converter into steady state almost instantaneously. The output of the opamp is buffered and connected to the current sense comparator using a 15:1 divider. The buffer helps to prevent the integrator capacitor from discharging during the PWM dimming state. Linear Dimming Linear dimming can be accomplished by varying the voltage at the IREF pin, as the output current is proportional to the voltage at the IREF pin. This can be done either by using a potentiometer from the REF pin or by applying an external voltage source at the IREF pin. Note: Due to the offset voltage of the transconductance opamp, pulling the IREFpin very close to GND will cause the internal short circuit comparator to trigger and shut down the IC. This limits the linear dimming range of the IC. However, a 1:10 linear dimming range can be easily obtained. It is recommended that the PWMD pin be used to get zero output current rather than pull the I REF pin to GND. FC9911 2012. 10. 31 11/13 Revision No : 0 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |