PCI6621 datasheet(134/204 Pages) TI

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5−22

5.20 ExCA Global Control Register

This register controls both PC Card sockets, and is not duplicated for each socket. The host interrupt mode bits in

this register are retained for 82365SL-DF compatibility. See Table 5−15 for a complete description of the register

contents.

Bit

Name

ExCA global control

Type

Default

ExCA global control

Offset:

CardBus Socket Address + 81Eh:

Card A ExCA Offset 1Eh

Card B ExCA Offset 5Eh

Type:

Read-only, Read/Write

Default:

00h

Table 5−15. ExCA Global Control Register Description

BIT

SIGNAL

TYPE

FUNCTION

7−5

RSVD

These bits return 0s when read. Writes have no effect.

INTMODEB

Level/edge interrupt mode select, card B. This bit selects the signaling mode for the PCI6x21/PCI6x11 host

interrupt for card B interrupts. This bit is encoded as:

0 = Host interrupt is edge mode (default).

1 = Host interrupt is level mode.

INTMODEA

Level/edge interrupt mode select, card A. This bit selects the signaling mode for the PCI6x21/PCI6x11 host

interrupt for card A interrupts. This bit is encoded as:

0 = Host interrupt is edge-mode (default).

1 = Host interrupt is level-mode.

2 ‡

IFCMODE

Interrupt flag clear mode select. This bit selects the interrupt flag clear mechanism for the flags in the ExCA

card status change register. This bit is encoded as:

0 = Interrupt flags cleared by read of CSC register (default)

1 = Interrupt flags cleared by explicit writeback of 1

1 ‡

CSCMODE

Card status change level/edge mode select. This bit selects the signaling mode for the

PCI6x21/PCI6x11 host interrupt for card status changes. This bit is encoded as:

0 = Host interrupt is edge-mode (default).

1 = Host interrupt is level-mode.

0 ‡

PWRDWN

Power-down mode select. When this bit is set to 1, the PCI6x21/PCI6x11 controller is in power-down

mode. In power-down mode the PCI6x21/PCI6x11 card outputs are placed in a high-impedance state until

an active cycle is executed on the card interface. Following an active cycle the outputs are again placed

in a high-impedance state. The PCI6x21/PCI6x11 controller still receives functional interrupts and/or card

status change interrupts; however, an actual card access is required to wake up the interface. This bit is

encoded as:

0 = Power-down mode disabled (default)

1 = Power-down mode enabled

‡ One or more bits in this register are cleared only by the assertion of GRST.

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