PCI6621 datasheet(159/204 Pages) TI

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7−15

7.23 Diagnostic Register

This register programs the M and N inputs to the PLL and enables the diagnostic modes. The default values for M

and N in this register set the PLL output to be 80 MHz, which is divided to get the 40 MHz and 20 MHz needed by

the flash media cores. See Table 7−16 for a complete description of the register contents. All bits in this register are

reset by GRST only.

Bit

Name

Diagnostic

Type

R/W

Default

Bit

Name

Diagnostic

Type

R/W

Default

Diagnostic

Type:

Read-only, Read/Write

Offset:

54h

Default:

0000 0305h

Table 7−16. Diagnostic Register Description

BIT

SIGNAL

TYPE

FUNCTION

31−17

TBD_CTRL

PLL control bits. These bits are reserved for PLL control and test bits.

DIAGNOSTIC

Diagnostic test bit. This test bit shortens the PLL clock CLK_VALID time and shortens the card detect

debounce times for simulation and TDL.

15−11

RSVD

Reserved. Bits 15−11 return 0s when read.

10−8

PLL_N

PLL_N input. The default value of this field is 03h.

7−5

RSVD

Reserved. Bits 7−5 return 0s when read.

4−0

PLL_M

PLL_M input. The default value of this field is 05h.

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