PCI6421 datasheet(58/204 Pages) TI

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3−10

Table 3−7. PCI6x21/PCI6x11 Registers Used to Program Serial-Bus Devices

PCI OFFSET

DESCRIPTION

B0h

Serial-bus data

Contains the data byte to send on write commands or the received data byte on read commands.

B1h

Serial-bus index

The content of this register is sent as the word address on byte writes or reads. This register is not used

in the quick command protocol.

B2h

Serial-bus slave

address

Write transactions to this register initiate a serial-bus transaction. The slave device address and the

R/W command selector are programmed through this register.

B3h

Serial-bus control

and status

Read data valid, general busy, and general error status are communicated through this register. In

addition, the protocol-select bit is programmed through this register.

3.6.3

Serial-Bus Interface Protocol

The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3−3.

The PCI6x21/PCI6x11 controller, which supports up to 100-Kb/s data-transfer rate, is compatible with standard mode

I2C using 7-bit addressing.

All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start

condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as shown

in Figure 3−6. The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high

transition of SDA while SCL is in the high state, as shown in Figure 3−6. Data on SDA must remain stable during the

high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control

signals, that is, a start or a stop condition.

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 3−6. Serial-Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is

unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by

the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−7

illustrates the acknowledge protocol.

SCL From

Master

123

SDA Output

By Transmitter

SDA Output

By Receiver

Figure 3−7. Serial-Bus Protocol Acknowledge

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