PCI6421 datasheet(115/204 Pages) TI

115 / 204 page

5−3

Table 5−1. ExCA Registers and Offsets

EXCA REGISTER NAME

PCI MEMORY ADDRESS

OFFSET (HEX)

EXCA OFFSET

(CARD A)

EXCA OFFSET

(CARD B)

Identification and revision ‡

800

Interface status

801

Power control †

802†

Interrupt and general control †

803†

Card status change †

804†

Card status change interrupt configuration †

805†

Address window enable

806

I / O window control

807

I / O window 0 start-address low-byte

808

I / O window 0 start-address high-byte

809

I / O window 0 end-address low-byte

80A

I / O window 0 end-address high-byte

80B

I / O window 1 start-address low-byte

80C

I / O window 1 start-address high-byte

80D

I / O window 1 end-address low-byte

80E

I / O window 1 end-address high-byte

80F

Memory window 0 start-address low-byte

810

Memory window 0 start-address high-byte

811

Memory window 0 end-address low-byte

812

Memory window 0 end-address high-byte

813

Memory window 0 offset-address low-byte

814

Memory window 0 offset-address high-byte

815

Card detect and general control †

816

Reserved

817

Memory window 1 start-address low-byte

818

Memory window 1 start-address high-byte

819

Memory window 1 end-address low-byte

81A

Memory window 1 end-address high-byte

81B

Memory window 1 offset-address low-byte

81C

Memory window 1 offset-address high-byte

81D

Global control ‡

81E

Reserved

81F

Memory window 2 start-address low-byte

820

Memory window 2 start-address high-byte

821

Memory window 2 end-address low-byte

822

Memory window 2 end-address high-byte

823

Memory window 2 offset-address low-byte

824

Memory window 2 offset-address high-byte

825

† One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared

by the assertion of PRST or GRST.

‡ One or more bits in this register are cleared only by the assertion of GRST.

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