PCI6421 datasheet(181/204 Pages) TI

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9−3

9.3

Command Register

The command register provides control over the Smart Card controller interface to the PCI bus. All bit functions

adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. The SERR_EN

and PERR_EN enable bits in this register are internally wired-OR between other functions, and these control bits

appear separately according to their software function. See Table 9−2 for a complete description of the register

contents.

Bit

Name

Command

Type

Default

Command

Offset:

04h

Type:

Read/Write, Read-only

Default:

0000h

Table 9−2. Command Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15−11

RSVD

Reserved. Bits 15−11 return 0s when read.

INT_DIS

INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.

0 = INTx assertion is enabled (default)

1 = INTx assertion is disabled

FBB_EN

Fast back-to-back enable. The Smart Card interface does not generate fast back-to-back transactions;

therefore, bit 9 returns 0 when read.

SER_EN

System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR

can be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 (PERR_EN)

must be set for this function to report address parity errors.

0 = Disable SERR output driver (default)

1 = Enable SERR output driver

RSVD

Reserved. Bit 7 returns 0 when read.

PERR_EN

Parity error response enable. Bit 6 controls this function response to parity errors through PERR. Data

parity errors are indicated by asserting PERR, whereas address parity errors are indicated by

asserting SERR.

0 = This function ignores detected parity error (default)

1 = This function responds to detected parity errors

VGA_EN

VGA palette snoop enable. The Smart Card interface does not feature VGA palette snooping;

therefore, bit 5 returns 0 when read.

MWI_EN

Memory write and invalidate enable. The Smart Card controller does not generate memory write

invalidate transactions; therefore, bit 4 returns 0 when read.

SPECIAL

Special cycle enable. The Smart Card interface does not respond to special cycle transactions;

therefore, bit 3 returns 0 when read.

MAST_EN

Bus master enable. This function is target only.

MEM_EN

Memory space enable. This bit controls memory access.

0 = Disables this function from responding to memory space accesses (default)

1 = Enables this function to respond to memory space accesses

IO_EN

I/O space enable. The Smart Card interface does not implement any I/O-mapped functionality;

therefore, bit 0 returns 0 when read.

PCI6421 Datasheet(PDF) 181 Page - Texas Instruments

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