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C8051F310/1/2/3/4/5/6/7
22
Rev. 1.6
Figure 1.4. C8051F313 Block Diagram
UART
8 kB
FLASH
256 byte
SRAM
POR
SFR Bus
8
0
5
1
C
o
r
e
Reset
/RST/C2CK
External
Oscillator
Circuit
Debug HW
Brown-
Out
Analog/Digital
Power
P
0
D
r
v
1K byte
SRAM
XTAL1
XTAL2
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
SPI
VDD
GND
C
R
O
S
S
B
A
R
P
1
D
r
v
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Port 0
Latch
SMBus
Timer
0,1,2,3 /
RTC
Port 1
Latch
2%
Internal
Oscillator
System Clock
P
2
D
r
v
P
3
D
r
v
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
10-bit
200ksps
ADC
A
M
U
X
AIN0-AIN20
VREF
VDD
CP1
+
-
Temp
VDD
CP0
+
-
C2D
Port 2
Latch
Port 3
Latch
PCA/
WDT