Rev. 1.6
37
C8051F310/1/2/3/4/5/6/7
4.
Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F31x
Name
Pin Numbers
Type
Description
‘F310/2/4 ‘F311/3/5 ‘F316/7
VDD
4
4
4
Power Supply Voltage.
GND
3
3
3
Ground.
RST/
C2CK
5
5
5
D I/O
D I/O
Device Reset. Open-drain output of internal POR. An
external source can initiate a system reset by driving
this pin low for at least 10 µs.
Clock signal for the C2 Debug Interface.
P3.0/
C2D
6
6
6
D I/O
D I/O
Port 3.0. See Section 13 for a complete description.
Bi-directional data signal for the C2 Debug Interface.
P0.0/
VREF
2
2
2
D I/O
A In
Port 0.0. See Section 13 for a complete description.
External VREF input. (‘F310/1/2/3 only)
P0.1
1
1
1
D I/O
Port 0.1. See Section 13 for a complete description.
P0.2/
XTAL1
32
28
24
D I/O
A In
Port 0.2. See Section 13 for a complete description.
External Clock Input. This pin is the external oscillator
return for a crystal or resonator.
P0.3/
XTAL2
31
27
23
D I/O
A Out or
D In
Port 0.3. See Section 13 for a complete description.
External Clock Output. For an external crystal or reso-
nator, this pin is the excitation driver. This pin is the
external clock input for CMOS, capacitor, or RC oscil-
lator configurations.
P0.4
30
26
22
D I/O
Port 0.4. See Section 13 for a complete description.
P0.5
29
25
21
D I/O
Port 0.5. See Section 13 for a complete description.
P0.6/
CNVSTR
28
24
20
Port 0.6. See Section 13 for a complete description.
ADC0 External Convert Start Input. (‘F310/1/2/3 only)
P0.7
27
23
19
D I/O
Port 0.7. See Section 13 for a complete description.
P1.0
26
22
18
D I/O or
A In
Port 1.0. See Section 13 for a complete description.
P1.1
25
21
17
D I/O or
A In
Port 1.1. See Section 13 for a complete description.
P1.2
24
20
16
D I/O or
A In
Port 1.2. See Section 13 for a complete description.
P1.3
23
19
15
D I/O or
A In
Port 1.3. See Section 13 for a complete description.
P1.4
22
18
14
D I/O or
A In
Port 1.4. See Section 13 for a complete description.
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