C8051F310 datasheet(8/224 Pages) ETC1

8 / 224 page

C8051F310/1/2/3/4/5/6/7

Rev. 1.6

7. Comparators

Figure 7.1. Comparator0 Functional Block Diagram ................................................ 67

Figure 7.2. Comparator1 Functional Block Diagram ................................................ 68

Figure 7.3. Comparator Hysteresis Plot ................................................................... 69

8. CIP-51 Microcontroller

Figure 8.1. CIP-51 Block Diagram............................................................................ 77

Figure 8.2. Memory Map .......................................................................................... 83

9. Reset Sources

Figure 9.1. Reset Sources...................................................................................... 103

Figure 9.2. Power-On and VDD Monitor Reset Timing .......................................... 104

10. Flash Memory

Figure 10.1. Flash Program Memory Map.............................................................. 111

11. External RAM

12. Oscillators

Figure 12.1. Oscillator Diagram.............................................................................. 117

Figure 12.2. 32.768 kHz External Crystal Example................................................ 122

13. Port Input/Output

Figure 13.1. Port I/O Functional Block Diagram ..................................................... 125

Figure 13.2. Port I/O Cell Block Diagram ............................................................... 126

Figure 13.3. Crossbar Priority Decoder with No Pins Skipped ............................... 127

Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 128

14. SMBus

Figure 14.1. SMBus Block Diagram ....................................................................... 141

Figure 14.2. Typical SMBus Configuration ............................................................. 142

Figure 14.3. SMBus Transaction ............................................................................ 143

Figure 14.4. Typical SMBus SCL Generation......................................................... 147

Figure 14.5. Typical Master Transmitter Sequence................................................ 153

Figure 14.6. Typical Master Receiver Sequence.................................................... 154

Figure 14.7. Typical Slave Receiver Sequence...................................................... 155

Figure 14.8. Typical Slave Transmitter Sequence.................................................. 156

15. UART0

Figure 15.1. UART0 Block Diagram ....................................................................... 159

Figure 15.2. UART0 Baud Rate Logic .................................................................... 160

Figure 15.3. UART Interconnect Diagram .............................................................. 161

Figure 15.4. 8-Bit UART Timing Diagram............................................................... 161

Figure 15.5. 9-Bit UART Timing Diagram............................................................... 162

Figure 15.6. UART Multi-Processor Mode Interconnect Diagram .......................... 163

16. Enhanced Serial Peripheral Interface (SPI0)

Figure 16.1. SPI Block Diagram ............................................................................. 169

Figure 16.2. Multiple-Master Mode Connection Diagram ....................................... 172

Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 172

Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 172

Figure 16.5. Master Mode Data/Clock Timing ........................................................ 174

Figure 16.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 175

Figure 16.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 175

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