2

ICS932S202

0600A—08/04/03

Pin Descriptions

The ICS932S202 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs.This

chip provides all the clocks required for such a system.

Spread Spectrum may be enabled through I

simplifies EMI qualification without resorting to board design iterations or costly shielding.The ICS932S202 employs

a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature

variations.

General Description

Pin number

Pin name

Type

Description

1, 7, 13, 19, 25,

31, 36, 41, 45

GND

PWR

Ground pins

2

REF0

OUT

14.318MHz reference clock outputs at 3.3V

REF1

OUT

14.318MHz reference clock outputs at 3.3V

SEL24_48

IN

Logic input to select 24 or 48MHz for pin 26 output

4, 10, 16, 23,

28, 35

VDD

PWR

Power pins 3.3V

5

X1

IN

XTAL_IN 14.318MHz crystal input

6

X2

OUT

XTAL_OUT Crystal output

PCICLK0

OUT

PCI clock output at 3.3V. Synchronous to CPU clocks.

FS0

IN

Logic - input for frequency selection

PCICLK1

OUT

PCI clock output at 3.3V. Synchronous to CPU clocks.

FS1

IN

Logic - input for frequency selection

PCICLK2

OUT

PCI clock output at 3.3V. Synchronous to CPU clocks.

FS2

IN

Logic - input for frequency selection

PCICLK3

OUT

PCI clock output at 3.3V. Synchronous to CPU clocks.

FS3

IN

Logic - input for frequency selection

22, 21, 20, 18,

17, 15, 14

PCICLK (10:4)

OUT

PCI clock outputs at 3.3V. Synchronous to CPU clocks.

24

PD#

IN

This asynchronous input powers down the chip when drive

active(Low). The internal PLLs are disabled and all the

output clocks are held at a Low state.

26

24_48MHz

OUT

24 or 48MHz output selectable by

SEL24_48# (0=48MHz 1=24MHz)

48MHz

OUT/IN

Fixed 48MHz clock output. 3.3V

FS4

IN

Logic - input for frequency selection

29

SCLK

IN

Clock input of I

30

SDATA

I/O

Data pin for I

34, 33, 32

3V66 (2:0)

OUT

3.3V clock outputs. These outputs are stopped when

CPU_STOP# is driven active..

38, 37

CPU_CSCLK (1:0)

OUT

Chipset clock outputs @ 2.5V

40, 42

CPUCLK (1:0)

OUT

CPU clock outputs @ 2.5V.

39, 43

VDDLCPU

PWR

Power pins for CPUCLKs. 2.5V

44, 46, 47

IOAPIC (2:0)

OUT

IOAPIC clocks @ 2.5V. Synchronous with CPUCLKs.

48

VDDLAPIC

PWR

Power pin for the IOAPIC outputs. 2.5V.

27

12

3

8

9

11