X9521 datasheet(11/25 Pages) INTERSIL

11 / 25 page

FN8207.1

August 25, 2005

Random EEPROM Read

Random read operation allows the master to access any

memory location in the array. Prior to issuing the Slave

Address Byte with the R/W bit set to one, the master

must first perform a “dummy” write operation. The master

issues the START condition and the Slave Address Byte,

receives an ACKNOWLEDGE, then issues an Address

Byte. This “dummy” Write operation sets the address

pointer to the address from which to begin the random

EEPROM read operation.

After the X9521 acknowledges the receipt of the Address

Byte, the master immediately issues another START

condition and the Slave Address Byte with the R/W bit

set to one. This is followed by an ACKNOWLEDGE from

the X9521 and then by the eight bit word. The master ter-

minates the read operation by not responding with an

ACKNOWLEDGE and instead issuing a STOP condition

(Refer to Figure 15.).

A similar operation called “Set Current Address” also

exists. This operation is performed if a STOP is issued

instead of the second START shown in Figure 15. In this

case, the device sets the address pointer to that of the

Address Byte, and then goes into standby mode after the

STOP bit. All bus activity will be ignored until another

START is detected.

Sequential EEPROM Read

Sequential reads can be initiated as either a current

address read or random address read. The first Data

Byte is transmitted as with the other modes; however,

the master now responds with an ACKNOWLEDGE,

indicating it requires additional data. The X9521 contin-

ues to output a Data Byte for each ACKNOWLEDGE

received. The master terminates the read operation by

not responding with an ACKNOWLEDGE and instead

issuing a STOP condition.

The data output is sequential, with the data from

address n followed by the data from address n + 1. The

address counter for read operations increments through

the entire memory contents to be serially read during

one operation. At the end of the address space the

counter “rolls over” to address 00h and the device con-

tinues to output data for each ACKNOWLEDGE

received (Refer to Figure 16.).

Slave

Address

Byte

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Figure 15. Random EEPROM Address Read Sequence

0 1 0 0 0 0

1 0 1 0 0 0 0

READ Operation

WRITE Operation

“Dummy” Write

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(n - 1)

(n is any integer greater than 1)

Data

(1)

Figure 16. Sequential EEPROM Read Sequence

0 0 0

X9521

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