HT46C62 datasheet(18/46 Pages) HOLTEK

18 / 46 page

HT46R62/HT46C62

Rev. 1.60

July 14, 2005

in a counting error. Blocking of the clock should be taken

into account by the programmer. It is strongly recom-

mended to load a desired value into the TMR register

first, before turning on the related timer/event counter,

for proper operation since the initial value of TMR is un-

known. Due to the timer/event scheme, the programmer

should pay special attention on the instruction to enable

then disable the timer for the first time, whenever there

is a need to use the timer/event function, to avoid unpre-

dictable result. After this procedure, the timer/event

function can be operated normally.

The bit0~bit2 of the TMRC can be used to define the

pre-scaling stages of the internal clock sources of

timer/event counter. The definitions are as shown. The

overflow signal of timer/event counter can be used to

generate the PFD signal. The timer prescaler is also

used as the PWM counter.

Input/Output Ports

There are 20 bidirectional input/output lines in the

microcontroller, labeled as PA, PB0~PB5, PD0~PD2

and PD4~PD6, which are mapped to the data memory

of [12H], [14H] and [18H] respectively. All of these I/O

ports can be used for input and output operations. For

input operation, these ports are non-latching, that is, the

inputs must be ready at the T2 rising edge of instruction

²MOV A,[m]² (m=12H, 14H or 18H). For output operation,

all the data is latched and remains unchanged until the

output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PDC) to control the input/output configuration. With this

control register, CMOS output or Schmitt Trigger input

with or without pull-high resistor structures can be re-

configured dynamically under software control. To func-

tion as an input, the corresponding latch of the control

²1². The input source also depends

on the control register. If the control register bit is

²1²,

the input will read the pad state. If the control register bit

²0², the contents of the latches will move to the inter-

nal bus. The latter is possible in the

²read-modify-write²

instruction.

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H and 19H.

After a chip reset, these input/output lines remain at high

levels or floating state (depending on pull-high options).

Each bit of these input/output latches can be set or

cleared by

²SET [m].i² and ²CLR [m].i² (m=12H, 14H or

18H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. Each I/O port has a pull-high option. Once the

pull-high option is selected, the I/O port has a pull-high

resistor, otherwise, there

¢s none. Take note that a

non-pull-high I/O port operating in input mode will cause

a floating state.

The PA3 is pin-shared with the PFD signal. If the PFD

option is selected, the output signal in output mode of

PA3 will be the PFD signal generated by timer/event

counter overflow signal. The input mode always retain

its original functions. Once the PFD option is selected,

the PFD output signal is controlled by PA3 data register

only. Writing

²1² to PA3 data register will enable the PFD

output function and writing 0 will force the PA3 to remain

²0². The I/O functions of PA3 are shown below.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PFD)

O/P

(PFD)

PA3

Logical

Input

Logical

Output

Logical

Input

PFD

(Timer on)

Note:

The PFD frequency is the timer/event counter

overflow frequency divided by 2.

The PA0, PA1, PA3, PD4, PD5 and PD6 are pin-shared

with BZ, BZ, PFD, INT0, INT1 and TMR pins respec-

tively.

The PA0 and PA1 are pin-shared with BZ and BZ signal,

respectively. If the BZ/BZ option is selected, the output

signal in output mode of PA0/PA1 will be the buzzer sig-

nal generated by multi-function timer. The input mode

always remain in its original function. Once the BZ/BZ

option is selected, the buzzer output signal are con-

trolled by the PA0, PA1 data register only.

The I/O function of PA0/PA1 are shown below.

PA0 I/O

OOOOOOOO

PA1 I/O

OOOOO

PA0 Mode

X C B

B C B

PA1 Mode

X C X

X C C C B

PA0 Data

X D

1 D0 0101

PA1 Data

X D X

X D1 D D X

PA0 Pad Status

B D0 0B0B

PA1 Pad Status

I D1 DD 0 B

Note:

²I² input; ²O² output

²D, D0, D1² Data

²B² buzzer option, BZ or BZ

²X² don¢t care

²C² CMOS output

The PB can also be used as A/D converter inputs. The

A/D function will be described later. There is a PWM

function shared with PD0/PD1/PD2. If the PWM function

is enabled, the PWM0/PWM1/PWM2 signal will appear

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