LMX9820ASM datasheet(17/44 Pages) NSC

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8.0 Digital Smart Radio (Continued)

8.0 Digital Smart Radio

8.1 FUNCTIONAL DESCRIPTION

The integrated Digital Smart Radio uses a heterodyne re-

ceiver architecture with a low intermediate frequency (2

MHz), such that the intermediate frequency filters can be in-

tegrated on-chip. The receiver consists of a low-noise am-

plifier (LNA) followed by two mixers. The intermediate

frequency signal processing blocks consist of a poly-phase

bandpass filter (BPF), two hard limiters (LIM), a frequency

discriminator (DET), and a post-detection filter (PDF). The

received signal level is detected by a received signal

strength indicator (RSSI).

The received frequency equals the local oscillator frequen-

cy (fLO) plus the intermediate frequency (fIF):

fRF = fLO + fIF (supradyne).

The radio includes a synthesizer consisting of a phase de-

tector, a charge pump, an (off-chip) loop filter, an RF fre-

quency divider, and a voltage-controlled oscillator (VCO).

The transmitter uses IQ-modulation with bit-stream data

that is gaussian filtered. Other blocks included in the trans-

mitter are a VCO buffer and a power amplifier (PA).

8.2 RECEIVER FRONT END

The receiver front end consists of a low-noise amplifier

(LNA) followed by two mixers and two low-pass filters for the

I- and Q-channels.

The intermediate frequency (IF) part of the receiver front

end consists of two IF amplifiers that receive input signals

from the mixers, delivering balanced I- and Q-signals to the

poly-phase bandpass filter. The poly-phase bandpass filter

is directly followed by two hard limiters that together gener-

ate an AD-converted RSSI signal.

8.2.1 Poly-Phase Bandpass Filter

The purpose of the IF bandpass filter is to reject noise and

spurious (mainly adjacent channel) interference that would

otherwise enter the hard-limiting stage. In addition, it han-

dles image rejection.

The bandpass filter uses both the I- and Q-signals from the

mixers. The out-of-band suppression should be higher than

40 dB (f < 1 MHz, f > 3 MHz). The bandpass filter is tuned

over process spread and temperature variations by the au-

totuner circuitry. A 5th-order Butterworth filter is used.

8.2.2 Hard Limiter and RSSI

The I- and Q-outputs of the bandpass filter are each fol-

lowed by a hard-limiter. The hard-limiter has its own refer-

ence current. The RSSI (Received

Signal

Strength

Indicator) reports the level of the RF input signal.

The RSSI is generated by piece-wise linear approximation

of the level of the RF signal. The RSSI has a mV/dB scale,

and an analog-to-digital converter for processing by the

baseband circuit. The input RF power is converted to a 5-bit

value. The RSSI value is then proportional to the input pow-

er (in dBm).

The digital output from the ADC is sampled on the BPK-

TCTL signal low-to-high transition.

8.3 RECEIVER BACK END

The hard limiters are followed by two frequency discrimina-

tors. The I-frequency discriminator uses the 90o phase-

shifted signal from the Q-path, while the Q-discriminator

uses the 90o phase-shifted signal from the I-path. A poly-

phase bandpass filter performs the required phase shifting.

The output signals of the I- and Q-discriminator are sub-

tracted and filtered by a low-pass filter. An equalizer is add-

ed to improve the eye-pattern for 101010 patterns.

After equalization, a dynamic AFC (automatic frequency off-

set compensation) circuit and slicer extract the RX_DATA

from the analog data pattern. The Eb/No of the demodulator

is approximately 17 dB.

8.3.1 Frequency Discriminator

The frequency discriminator gets its input signals from the

limiter. A defined signal level (independent of the power

supply voltage) is needed to obtain the input signal. Both in-

puts of the frequency discriminator have limiting circuits to

optimize performance. The bandpass filter in the frequency

discriminator is tuned by the autotuning circuitry.

8.3.2 Post-Detection Filter and Equalizer

The output signals of the FM discriminator go through a

post-detection filter followed by an equalizer. Both the post-

detection filter and equalizer are tuned to the proper fre-

quency by the autotuning circuitry. The post-detection filter

is a low-pass filter intended to suppress all remaining spuri-

ous signals, such as the second harmonic (4 MHz) from the

FM detector and noise generated after the limiter.

The post-detection filter also helps for attenuating the first

adjacent channel signal. The equalizer improves the eye-

opening for 101010 patterns. The post-detection filter is a

third-order Butterworth filter.

8.4 AUTOTUNING CIRCUITRY

The autotuning circuitry is used for tuning the bandpass fil-

ter, detector, post-detection filter, equalizer, and transmit fil-

ters for process and temperature variations. The circuitry

includes offset compensation for the FM detector.

8.5 SYNTHESIZER

The synthesizer consists of a phase-frequency detector, a

charge pump, a low-pass loop filter, a programmable fre-

quency divider, a voltage-controlled oscillator (VCO), a del-

ta-sigma modulator, and a lookup table.

The frequency divider consists of a divide-by-2 circuit (di-

vides the 5 GHz signal from the VCO down to 2.5 GHz), a

divide-by-8-or-9 divider, and a digital modulus control. The

delta-sigma modulator controls the division ratio and also

generates an input channel value to the lookup table.

8.5.1 Phase-Frequency Detector

The phase-frequency detector is a 5-state phase-detector.

It responds only to transitions, hence phase-error is inde-

LMX9820ASM Datasheet(PDF) 17 Page - National Semiconductor (TI)

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