DS280DF810 datasheet(41/51 Pages) TI1

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DS280DF810

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SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019

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10 Power Supply Recommendations

Follow these general guidelines when designing the power supply:

1. The power supply should be designed to provide the recommended operating conditions outlined in

Specifications in terms of DC voltage, AC noise, and start-up ramp time.

2. The maximum current draw for the DS280DF810 is provided in Specifications . This figure can be used to

calculate the maximum current the supply must provide. Typical mission-mode current draw can be inferred

from the typical power consumption in Specifications.

3. The DS280DF810 does not require any special power supply filtering (that is, ferrite bead) provided the

recommended operating conditions are met. Only standard supply decoupling is required. Refer to Pin

Configuration and Functions for details concerning the recommended supply decoupling.

11 Layout

11.1 Layout Guidelines

The following guidelines should be followed when designing the layout:

1. Decoupling capacitors should be placed as close to the VDD pins as possible. Placing them directly

underneath the device is one option if the board design permits.

2. High-speed differential signals TXnP/TXnN and RXnP/RXnN should be tightly coupled, skew matched, and

impedance controlled.

3. Vias should be avoided when possible on the high-speed differential signals. When vias must be used, care

should be taken to minimize the via stub, either by transitioning through most or all layers, or by back drilling.

4. GND relief can be used beneath the high-speed differential signal pads to improve signal integrity by

counteracting the pad capacitance.

5. GND vias should be placed directly beneath the device connecting the GND plane attached to the device to

the GND planes on other layers. This has the added benefit of improving thermal conductivity from the

device to the board

6. BGA landing pads for a 0.8 mm pitch flip-chip BGA are typically 0.4 mm in diameter (exposed). The actual

size of the copper pad will depend on whether solder-mask-defined (SMD) or non-solder-mask-defined

solder land pads are used. For more information, refer to TI’s Surface Mount Technology (SMT) References

at http://focus.ti.com/quality/docs under the "Quality and Lead (Pb)-Free Data" menu.

7. If vias are used for the high-speed signals, ground via should be implemented adjacent to the signal via to

provide return path and isolation. For differential pair, the typical via configuration is "ground-signal-signal-

ground."

11.2 Layout Example

The following example layout demonstrates how all signals can be escaped from the BGA array using stripline

routing on a generic 28-layer stackup. This example layout assumes the following:

•

Trace width: 0.127 mm (5 mil)

•

Trace edge-to-edge spacing: 0.152 mm (6 mil)

•

VIA finished hole size (diameter): 0.203 mm (8 mil)

•

VIA drilled hole size: 0.254 mm (10 mil)

•

VIA-to-VIA spacing: 1.0 mm (39 mil), to enhance PCB manufacturability

•

No VIA-in-pad used

Note that many other escape routing options exist using different trace width and spacing combinations. The

optimum trace width and spacing will depend on the PCB material, PCB routing density, and other factors.

DS280DF810 Datasheet(PDF) 41 Page - Texas Instruments

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