DS280DF810ABVT datasheet(16/51 Pages) TI1

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DS280DF810

SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019

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8 Detailed Description

8.1 Overview

The DS280DF810 is an eight-channel multi-rate retimer with integrated signal conditioning. Each of the eight

channels operates independently. Each channel includes a continuous-time linear equalizer (CTLE) and a

Decision Feedback Equalizer (DFE), which together compensate for the presence of a dispersive transmission

channel between the source transmitter and the DS280DF810 receiver. The CTLE and DFE are self-adaptive.

Each channel includes an independent voltage-controlled oscillator (VCO) and phase-locked loop (PLL) which

produce a clean clock that is frequency-locked to the clock embedded in the input data stream. The high-

frequency jitter on the incoming data is attenuated by the PLL, producing a clean clock with substantially-reduced

jitter. This clean clock is used to re-time the incoming data, removing high-frequency jitter from the data stream

and reproducing the data on the output with significantly-reduced jitter.

Each channel of the DS280DF810 features an output driver with adjustable differential output voltage and output

equalization in the form of a three-tap finite impulse response (FIR) filter. The output FIR compensates for

dispersion in the transmission channel at the output of the DS280DF810.

All transmit and receive channels on the DS280DF810 are AC-coupled with physical AC-coupling capacitors (220

nF +/- 20%) on the package substrate. This ensures common mode voltage compatibility with all link partners

and eliminates the need for AC coupling capacitors on the system PCB, thereby saving cost and greatly reducing

PCB routing complexity.

Between each group of two adjacent channels (e.g. between channels 0–1, 2–3, 4–5, and 6–7) is a full 2x2

cross-point switch. This allows multiplexing and de-multiplexing and fanout applications for fail-over redundancy,

as well as cross-over applications to aid PCB routing.

Each channel also includes diagnostic features such as a Pseudo Random Bit Sequence (PRBS) pattern

generator and checker, as well as a non-destructive eye opening monitor (EOM). The EOM can be used to plot

the post-equalized eye at the input to the decision slicer or simply to read the horizontal eye opening (HEO) and

vertical eye opening (VEO).

The DS280DF810 is configurable through a single SMBus port. The DS280DF810 can also act as an SMBus

master to configure itself from an EEPROM. Up to sixteen DS280DF810 devices can share a single SMBus.

The sections which follow describe the functionality of various circuits and features within the DS280DF810. For

more information about how to program or operate these features, consult the DS280DF810 Programming

Guide.

DS280DF810ABVT Datasheet(PDF) 16 Page - Texas Instruments