DS280DF810ABVT datasheet(37/51 Pages) TI1

37 / 51 page

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x8 25 G / 28 G - LR

Mezzanine

DS280DF810

Mezzanine

x8 25 G SR / 28 G - LR

ASIC

FPGA

DS280DF810

Optical

Optical or Copper

Optical

25 G / 28 G

VSR

25 G / 28 G

VSR

DS280DF810

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SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019

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9.2.2 Front-Port Jitter Cleaning Application

The DS280DF810 has strong equalization capabilities that allow it to equalize insertion loss, reduce jitter, and

extend the reach of front-port interfaces. A single DS280DF810 can be used to support all eight egress channels

for a stacked QSFP cage. Another DS280DF810 can be used to support all eight ingress channels for the same

stacked QSFP cage. Alternatively, a single DS280DF810 can be used to support all egress and ingress channels

for a single QSFP port.

For applications which require IEEE802.3 100GBASE-CR4 or 25GBASE-CR auto-negotiation and link training, a

linear repeater device such as the DS280BR820 (or similar) is recommended.

Figure 18 illustrates this configuration, and Timing Requirements, Retimer Jitter Specifications shows an example

simplified schematic for a typical front-port application.

Figure 18. Front-Port Application Block Diagram

DS280DF810ABVT Datasheet(PDF) 37 Page - Texas Instruments