DS280DF810ABVT datasheet(5/51 Pages) TI1

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DS280DF810

www.ti.com

SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019

Product Folder Links: DS280DF810

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Pin Functions (continued)

TYPE

INTERNAL

PULL-UP/

PULL-DOWN

DESCRIPTION

NAME

NO.

TX1P

H13

Output

None

Inverting and non-inverting 50

Ω driver outputs. These outputs are

AC coupled on-chip with physical 220 nF capacitors.

TX1N

J13

Output

None

TX2P

H11

Output

None

Inverting and non-inverting 50

Ω driver outputs. These outputs are

AC coupled on-chip with physical 220 nF capacitors.

TX2N

J11

Output

None

TX3P

Output

None

Inverting and non-inverting 50

Ω driver outputs. These outputs are

AC coupled on-chip with physical 220 nF capacitors.

TX3N

Output

None

TX4P

Output

None

Inverting and non-inverting 50

Ω driver outputs. These outputs are

AC coupled on-chip with physical 220 nF capacitors.

TX4N

Output

None

TX5P

Output

None

Inverting and non-inverting 50

Ω driver outputs. These outputs are

AC coupled on-chip with physical 220 nF capacitors.

TX5N

Output

None

TX6P

Output

None

Inverting and non-inverting 50

Ω driver outputs. These outputs are

AC coupled on-chip with physical 220 nF capacitors.

TX6N

Output

None

TX7P

Output

None

Inverting and non-inverting 50

Ω driver outputs. These outputs are

AC coupled on-chip with physical 220 nF capacitors.

TX7N

Output

None

CALIBRATION CLOCK PINS

CAL_CLK_IN

Input, 2.5 V

CMOS

Weak pull-down

25 MHz (±100 PPM) 2.5 V single-ended clock from external

oscillator. No stringent phase noise or jitter requirements on this

clock. Used to calibrate VCO frequency range. This clock is not

used to recover data.

CAL_CLK_OUT E15

Output, 2.5 V

CMOS

None

2.5 V buffered replica of calibration clock input (pin E1) for

connecting multiple devices in a daisy-chained fashion.

SYSTEM MANAGEMENT BUS (SMBUS) PINS

ADDR0

D13

Input, 4-level

None

4-level strap pins used to set the SMBus address of the device.

The pin state is read on power-up. The multi-level nature of these

pins allows for 16 unique device addresses. The four strap options

include:

0: 1 k

Ω to GND

R: 10 k

Ω to GND

F: Float

1: 1 k

Ω to VDD

Refer to Device SMBus Address for more information.

ADDR1

E13

Input, 4-level

None

EN_SMB

Input, 4-level

None

Four-level 2.5 V input used to select between SMBus master mode

(float) and SMBus slave mode (high). The four defined levels are:

0: 1 k

Ω to GND - RESERVED, TI test mode.

R: 10 k

Ω to GND - RESERVED, TI test mode

F: Float - SMBus Master Mode

1: 1 k

Ω to VDD - SMBus Slave Mode

SDA

E12

I/O, 3.3 V

LVCMOS, Open

Drain

None

SMBus data input and open drain output. External 2 k

Ω to 5 kΩ

pull-up resistor is required as per SMBus interface standard. This

pin is 3.3 V LVCMOS tolerant.

SDC

F12

I/O, 3.3 V

LVCMOS, Open

Drain

None

SMBus clock input and open drain clock output. External 2 k

Ω to 5

Ω pull-up resistor is required as per SMBus interface standard.

This pin is 3.3 V LVCMOS tolerant.

DS280DF810ABVT Datasheet(PDF) 5 Page - Texas Instruments

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