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DS280DF810ABVT Datasheet(PDF) 33 Page - Texas Instruments |
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DS280DF810ABVT Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 51 page ![]() Line Card Switch Fabric Card ASIC FPGA x8 25 G / 28 G x8 25 G / 28 G ASIC FPGA Passive Backplane/ Midplane 33 DS280DF810 www.ti.com SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019 Product Folder Links: DS280DF810 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Typical Application (continued) 9.2.1 Backplane and Mid-Plane Reach Extension Application The DS280DF810 has strong equalization capabilities that allow it to recover data over channels up to 35 dB insertion loss (at 12.9 GHz). As a result, the optimum placement for the DS280DF810 in a backplane and mid- plane application is with the higher-loss channel segment at the input and the lower-loss channel segment at the output. This reduces the equalization burden on the downstream ASIC/FPGA, as the DS280DF810 is equalizing a majority of the overall channel. This type of asymmetric placement is not a requirement, but when an asymmetric placement is required due to the presence of a passive backplane or mid-plane, then this becomes the recommended placement. Figure 16. Backplane and Mid-Plane Application Block Diagram |
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