DS280DF810ABVT datasheet(40/51 Pages) TI1

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DS280DF810

SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019

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7. Make provisions in the schematic and layout for a 25 MHz (±100 ppm) single-ended CMOS clock. Each

DS280DF810 retimer buffers the clock on the CAL_CLK_IN pin and presents the buffered clock on the

CAL_CLK_OUT pin. This allows multiple (up to 20) retimers’ calibration clocks to be daisy chained to avoid

the need for multiple oscillators on the board. If the oscillator used on the board has a 2.5 V CMOS output,

then no AC coupling capacitor or resistor ladder is required at the input to CAL_CLK_IN. No AC coupling or

resistor ladder is needed between one retimer’s CAL_CLK_OUT output and the next retimer’s CAL_CLK_IN

input. The final retimer’s CAL_CLK_OUT output can be left floating.

8. Connect the INT_N open-drain output to an FPGA or CPU if interrupt monitoring is desired. Note that

multiple retimers’ INT_N outputs can be connected together since this is an open-drain output. The common

INT_N net should be pulled high.

9. If the application requires initial CDR lock acquisition at the ambient temperature extremes defined in Timing

Requirements, Retimer Jitter Specifications, care should be taken to ensure the operating junction

temperature is met as well as the CDR stay-in-lock ambient temperature range defined in Timing

Requirements, Retimer Jitter Specifications. For example, if initial CDR lock acquisition occurs at an ambient

temperature of 85 ºC, then maintaining CDR lock would require the ambient temperature surrounding the

DS280DF810 to be kept above (85 ºC - TEMPLOCK-).

9.2.3 Application Curves

Figure 20. DS280DF810 Operating at 25.78125 Gbps

Figure 21. DS280DF810 FIR Transmit Equalization while

Operating at 25.78125 Gbps

Figure 20 shows a typical output eye diagram for the DS280DF810 operating at 25.78125 Gbps with PRBS9

pattern using FIR main-cursor of +18, pre-cursor of -1 and post-cursor of +2. All other device settings are left at

default.

Figure 21 shows an example of DS280DF810 FIR transmit equalization while operating at 25.78125 Gbps. In this

example, the Tx FIR filter main-cursor is set to +15, post-cursor to -3 and pre-cursor to -3. An 8T pattern is used

to evaluate the FIR filter, which consists of 0xFF00. All other device settings are left at default.

DS280DF810ABVT Datasheet(PDF) 40 Page - Texas Instruments