8143 datasheet(14/24 Pages) MAXWELL

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12-Bit Serial Daisy-Chain D/A Converter

8143

07.23.03 REV 3

The CLR input allows asynchronous resetting of the DAC register to 0000 0000 0000. This reset does not affect data

held in the input registers. While in unipolar mode, a CLEAR will result in the analog output going to 0V. In bipolar

mode, the output will go to -V

REF.

Interface Input Description

STB

1 (Pin 4), STB2 (Pin 8), STB4 (Pin 11) - Input register and buffered output strobe. Inputs active on falling edge.

Selected to load serial data into input register and buffered output stage. See Table 3 for details.

STB

3 (Pin 10) - Input register and buffered output strobe input. Active on falling edge. Selected to load serial data into

input register and buffered output stage. See Table 3 for details.

1 (Pin 5), LD2 (Pin 9) - Load DAC register inputs. Active low. Selected together to load contents of input register into

DAC register.

CLR (Pin 13) - Clear input. Active low. Asynchronous. When LOW, 12-bit DAC register is forced to a zero code (0000

0000 0000) regardless of other interface inputs.

FIGURE 15.

TIMING DIAGRAM

* Strobe waveform is inverted if STB

3 is used to strobe serial data bits into input register.

** Data is strobed into and out of the input shift register MSB first.

TABLE 1. TRUTH TABLE

INPUT REGISTER/DIGITAL

OUTPUT

CONTROL INPUTS

DAC

CONTROL INPUT

OPERATION

NOTES

STB4

STB3

STB2

STB1

CLR

LD2

LD1

Serial data bit loaded from

SRI into input register and

digital output (SRO pin)

after 12 clocked bits

1,2

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