8143 datasheet(16/24 Pages) MAXWELL

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12-Bit Serial Daisy-Chain D/A Converter

8143

07.23.03 REV 3

FIGURE 16. UNIPOLAR OPERATION WITH HIGH ACCURACY OP AMP (2-QUADRANT)

FIGURE 17. UNIPOLAR OPERATION WITH FAST OP AMP AND GAIN ERROR TRIMMING (2-QUADRANT)

In many applications, the 8143 zero scale error and low gain error, permit the elimination of external trimming compo-

nents without adverse effects on circuit performance.

For applications requiring a tighter gain error than 0.024% at 25°C for the top grade part, or 0.048% for the lower grade

part, the circuit in Figure 17 may be used. Gain error may be trimmed by adjusting R1.

The DAC register must first be loaded with all 1s. R1 is then adjusted until V

OUT = -VREF (4095/4096). In the case of an

adjustable V

REF, R1 and RFEEDBACK may be omitted, with VREF adjusted to yield the desired full-scale output.

Bipolar Operation (4-Quadrant)

Figure 18 details a suggested circuit for bipolar, or offset binary, operation. Table 5 shows the digital input-to-analog

output relationship. The circuit uses offset binary coding. Twos complement code can be converted to offset binary by

software inversion of the MSB or by the addition of an external inverter to the MSB input.

Resistor R3, R4 and R5 must be selected to match within 0.01% and must all be of the same (preferably metal foil)

type to assure temperature coefficient match. Mismatching between R3 and R4 causes offset and full-scale error.

Calibration is performed by loading the DAC register with 1000 0000 0000 and adjusting the ratio of R3 to R4 to yield

OUT = 0V. Full scale can be adjusted by loading the DAC register with 1111 1111 1111 and adjusting either the ampli-

tude of V

REF of the value of R5 until the desired VOUT is achieved.

8143 Datasheet(PDF) 16 Page - Maxwell Technologies