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DP159 Datasheet(PDF) 7 Page - Texas Instruments

Part # DP159
Description  as DisplayPort Retimer
PDF  15 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DP159 Datasheet(HTML) 7 Page - Texas Instruments

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background image
U2
Xilinx_FPGA
MGTRXP0
1
MGTRXN0
2
MGTRXP1
3
MGTRXN1
4
MGTRXP2
5
MGTRXN2
6
MGTRXP3
7
MGTRXPN
8
IO_L0P
9
IO_L0N
10
IO_L1P
11
IO_L1N
12
IO_L2P
13
IO_L2N
14
REFCLKINP
15
REFCLKINN
16
SCL_CTL
PG3
SDA_CTL
PG3
DP159_EN
PG3
R13
2K
0402
5%
R12
2K
0402
5%
AARDVARK
CONNECTOR
J2
Header 5x2 0.1" thru-hole
2
4
6
8
10
1
3
5
7
9
BOARD_3P3V
SDA_CTL
SCL_CTL
Sheet
of
SIZE
SCALE: NONE
DWG NO:
Xilinx FPGA
Friday, July 17, 2015
A
4
4
50-ohm pullups are
required for
OUT[2:0]P/N and
OUT_CLKP/N because
these lanes at TMDS
transmitters
PLACE CLOSE TO DP159 (U1).
C22
0.1uF C23
0.1uF
BOARD_3P3V
R6
49
r0201
1%
R7
49
r0201
1%
C24
0.1uF
C25
0.1uF
C26
0.1uF
C27
0.1uF
TXML2P
TXML1N
TXML1P
TXML0N
TXML0P
OUT_D2N
PG3
OUT_D2P
PG3
TXML3N
TXML3P
TXML2N
OUT_D0P
PG3
OUT_D1N
PG3
OUT_D1P
PG3
HPD
PG2
OUT_D0N
PG3
OUT_CLKN
PG3
OUT_CLKP
PG3
C29
0.1uF
C28
0.1uF
R8
49
r0201
1%
R9
49
r0201
1%
R10
49
r0201
1%
R11
49
r0201
1%
AUXP
PG2
AUXN
PG2
R5
49
r0201
1%
R4
49
r0201
1%
C30
0.1uF
C31
0.1uF
AUX_CLKP
PG3
AUX_CLKN
PG3
www.ti.com
Local I
2C Interface
Figure 8. Xilinx FPGA
7
SLLA358 – December 2015
DP159 as DisplayPort Retimer
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated



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