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Initial Power-up Configuration

4

Initial Power-up Configuration

The following registers must be programmed immediately after power-up or whenever OE transitions from

de-asserted (low) to asserted (high).

struct DP159InitT

{

unsigned short regAddr;

//DP159’s register address

unsigned short regValue;

//Data written

};

struct DP159InitT RBR_HBR_HBR2_Common_Init[] = {

//Page 0

{0xFF, 0x00} , //Select Page 0

{0x09, 0x36} , //Enable X-Mode

{0x0A, 0x7B} , //Disable HPD_SNK pass thru to HPD_SRC.

{0x0D, 0x80} , //Enable clock on AUX. Select 1/20 mode.

{0x0C, 0x6D} , //Set TX Swing to Max

{0x10, 0x00} , //Turn off pattern verifier

{0x16, 0xF1} , //Disable char-alignment on all lanes.

{0xFF, 0x01} , // Select Page 1

//CONFIGURE PLL BLOCK

{0x00, 0x02} , //Enable Bandgap.

{0x04, 0x80} , //PLL_FBDIV[7:0]

{0x05, 0x00} , //PLL_FBDIV[10:8]

{0x08, 0x00} ,

{0x0D, 0x02} , //Select LN0 for clock.

{0x0E, 0x03} , //CDR_CONFIG[4:0].

FIXED, LN0.

{0x01, 0x01} , //CP_EN is PLL mode

{0x02, 0x3F} , //CP_CURRENT is high.

{0x0B, 0x33} , //Loop Filter to 8K.

{0xA1, 0x02} , //Allows for Override of PLL settings.

{0xA4, 0x02} , //Allows for Override of PLL settings.

//CONFIGURE TX BLOCK

{0x10, 0xF0} , //ENTX for all four lanes (disable)

{0x11, 0x30} , //TX_RATE is Full Rate, TX_TERM = 75 to 150 , TX_INVPAIR = None

{0x14, 0x00} , //HDMI_TWPST1 is 0dB pre-emphasis

{0x12, 0x03} , //SLEW_CTRL is Normal, SWING is 600mV.

{0x13, 0xFF} , //FIR_UPD.

Load TX settings

{0x13, 0x00} ,

//CONFIGURE RX BLOCK

{0x30, 0xE0} , //Disable Receivers except lane 0

{0x32, 0x00} , //PD_RXINT

{0x31, 0x00} , //RX_RATE is Full

{0x4D, 0x08} , //EQFTC = 0 and EQLEV = 8

{0x4C, 0x01} , //Enable Fixed EQ

{0x34, 0x01} , //Enable Offset correction

{0x32, 0xF0} , //Load RX settings.

{0x32, 0x00} ,

{0x33, 0xF0} , //Load EQ settings.

{0xFF, 0x00} , //Select

Page 0

{0x0A, 0x3B} , //Enable HPD_SNK pass thru to HPD_SRC. Retimer

{0xFF, 0x01} , //Select

Page 1

};

9

SLLA358 – December 2015

DP159 as DisplayPort Retimer

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