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Initial Power-up Configuration

4.3.1

Determine PLL Locked

While the DP159 is receiving the TPS1 pattern, software must monitor the DP159’s PLL

LOCK_COMPLETE status. The PLL is considered locked when address 0x00 bit 6 in Page 1 is set. Note

that depending on the quality of signal being received, the DP159 may not acquire PLL lock until VOD

reaches level 1 or Level 2. Because of this, the lock_wait interval must be set to a value large enough to

allow the DP159 to acquire lock.

u16

lock_wait

= 256; //Approx 300us with 400KHz I2C.

ReadBuffer[0] = 0;

while (ReadBuffer[0] == 0 && lock_cnt < lock_wait) {

read_csr (0x00);

ReadBuffer[0] = ReadBuffer[0] & 0x40; // 0x80;

lock_cnt++;

}

4.3.2

Change PLL Mode

Once PLL lock has been achieved, software must immediately transition the PLL mode of operation from

PLL_MODE to PD_MODE. The actual PLL setting will be different based on the datarate. It is important to

note that A_LOCK_OVR (Page 1 address 0x00 bit 6) must be set to a 1’b1 before transitioning the PLL

mode. The following code shows what values based on datarate need to be programmed and the order to

program them. It is also important to enable the TX lanes in this stage so that DP sink can start

performing clock recovery.

struct DP159InitT

{

unsigned short regAddr;

//DP159’s register address

unsigned short regValue;

//Data written

};

rtxen = (link_lanecnt == 1) ? 0xE1 : (link_lanecnt == 2) ? 0xC3 : 0x0F;

struct DP159InitT RBR_CRDONE[] = {

{0x10, rtxen} , //Enable TX lanes

{0x00, 0x23} , //Enable PLL and Bandgap and A_LOCK_OVR

{0x02, 0x1F} , //CP_CURRENT for RBR.

{0x0B, 0x30} , //PLL Loop filter 1K.

{0x01, 0x02} , //CP_EN is PD mode

};

struct DP159InitT HBR_CRDONE[] = {

{0x10, rtxen} , //Enable TX lanes

{0x00, 0x23} , //Enable PLL and Bandgap and A_LOCK_OVR

{0x02, 0x27} , //CP_CURRENT for HBR

{0x0B, 0x30} , //PLL Loop filter 1K.

{0x01, 0x02} , //CP_EN is PD mode

};

struct DP159InitT HBR2_CRDONE[] = {

{0x10, rtxen} , //Enable TX lanes

{0x00, 0x23} , //Enable PLL and Bandgap and A_LOCK_OVR

{0x02, 0x5F} , //CP_CURRENT for HBR2.

{0x0B, 0x30} , //PLL Loop filter 1K.

{0x01, 0x02} , //CP_EN is PD mode

};

4.4

Link Training Channel Equalization Phase

After completing the clock recovery phase of link training, the source will transition to the channel

equalization phase. Once in the channel equalization phase, software should enable DP159 adaptive

equalizer.

write_csr (0x4C, 0x03);

// Enable Adaptive EQ

11

SLLA358 – December 2015

DP159 as DisplayPort Retimer

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