Initial Power-up Configuration

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4.1

Reinitialize PLL, RX, and TX Settings

The DP159 PLL, RX, and TX settings must be reinitialized anytime there is a change in datarate, lane

count, HPD de-asserted (sink removal), or DisplayPort Source no longer detected.

All registers below are located in DP159 Page 1.

struct DP159InitT

{

unsigned short regAddr;

//DP159’s register address

unsigned short regValue;

//Data written

};

struct DP159InitT Disconnect_Event[] = {

{0x00, 0x02} , //Disable PLL and clear A_LOCK_OVR

{0x34, 0x01} , //Enable Offset Correction

{0x02, 0x3F} , //CP_Current is High BW.

{0x01, 0x01} , //CP_EN is PLL mode

{0x0B, 0x33} , //PLL Loop filter 8K

{0x4D, 0x08} , //EQFTC = 0 and EQLEV = 8

{0x4C, 0x01} , //Set to Fixed EQ

{0x33, 0xF0} , //Load EQ settings

{0x10, 0xF0} , //Disable all Tx Lanes

{0x30, 0xE0} , //Enable Rx Lane 0 only

};

4.2

Bandwidth and Number of Lanes

Before the beginning of link training, the GPU must inform the sink of the link bandwidth (LINK_BW_SET)

and number of lanes (LANE_COUNT_SET). It is at this stage software must to program the DP159’s PLL

enable and number of Rx lanes. The TX lanes will be disabled in this step.

#define LBW_HBR2

0x14

// 0x14 = 20 -> 20 * 270 Mbps = 5.40 Gbps

#define LBW_HBR

0x0A

// 0x0A = 10 -> 10 * 270 Mbps = 2.70 Gbps

#define LBW_RBR

0x06

// 0x06 =

6 ->

6 * 270 Mbps = 1.62 Gbps

void BW_handler (void) {

u8

rtxen, eqreg, tsten;

u16 eq_lev = 8;

rtxen = (link_lanecnt == 1) ? 0xE1 : (link_lanecnt == 2) ? 0xC3 : 0x0F;

eqreg = ((link_bw == LBW_HBR2) ? 0x0 : (link_bw == LBW_HBR ) ? 0x1 : 0x2 )<< 4 | (eq_lev &

0x0F);

tsten = (link_lanecnt == 1) ? 0x11 : (link_lanecnt == 2) ? 0x31 : 0xF1;

write_csr (0x10, 0xF0);

// Disable TX lanes

write_csr (0x00, 0x02);

// Enable Bandgap, Disable PLL, clear A_LOCK_OVR

write_csr (0x01, 0x01);

// CP_EN = PLL (reference) mode

write_csr (0x0B, 0x33);

// Set PLL loop filter

write_csr (0x02, 0x3F);

// Set CP_CURRENT

write_csr (0x30, rtxen);

// Enable RX lanes

write_csr (0x00, 0x03);

// Enable Bandgap, Enable PLL, clear A_LOCK_OVR

write_csr (0x4C, 0x01);

// Enable fixed EQ (use fixed when RX disabled)

write_csr (0x4D, eqreg);

// Set EQFTC and EQLEV (fixed EQ)

}

4.3

Link Training Clock Recovery phase

While in the clock recovery phase of link training phase, the DisplayPort source is required to transmit a

TPS1 pattern. The TPS1 pattern consists of a repetition of D10.2 symbols (without scrambling). This

pattern results in a clock at ½ the datarate (2.7 GHz for HBR2, 1.35 GHz for HBR, and 810 MHz for RBR).

10

DP159 as DisplayPort Retimer

SLLA358 – December 2015

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