CC3230SF datasheet(13/104 Pages) TI

13 / 104 page

PINS

TYPE

DESCRIPTION

SELECT AS

WAKEUP

SOURCE

CONFIGURE

ADDITIONAL

ANALOG MUX

MUXED

WITH JTAG

NO.

NAME

GND_TAB

—

Thermal pad and electrical

ground

N/A

(1)

This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3230x device

between two antennas. These pins must not be used for other functionalities.

(2)

This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an

output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode

to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

(3)

Device firmware automatically enables the digital path during ROM boot.

(4)

Pin 45 is used by an internal DC/DC converter (ANA2_DCDC). This pin will be available automatically if the serial flash is forced in the

CC3230SF device. For the CC3230S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.

(5)

Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level

configuration is required to use pin 52 as a digital pad. Pin 52 is used for the RTC crystal in most applications. However, in some

applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available,

the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the device to

automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent

false detection, TI recommends using pin 52 for output-only functions.

(6)

This pin is shared by the ADC inputs and digital I/O pad cells.

(7)

To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-kΩ resistor.

(8)

Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always

connected and must be made Hi-Z before enabling the ADC switch.

Table 7-1. Pin Attributes

NO.

SIGNAL NAME(1)

SIGNAL

TYPE(2)

PIN MUX

ENCODING

SIGNAL

DIRECTION

PAD STATES

LPDS(3)

Hib(4)

nRESET = 0

GPIO10 (PN)

I/O

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

I2C_SCL

I/O (open drain)

Hi-Z, Pull, Drive

GT_PWM06

Hi-Z, Pull, Drive

UART1_TX

SDCARD_CLK

GT_CCP01

Hi-Z, Pull, Drive

GPIO11 (PN)

I/O

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

I2C_SDA

I/O (open drain)

Hi-Z, Pull, Drive

GT_PWM07

Hi-Z, Pull, Drive

pXCLK(XVCLK)

SDCARD_CMD

I/O (open drain)

Hi-Z, Pull, Drive

UART1_RX

Hi-Z, Pull, Drive

GT_CCP02

Hi-Z, Pull, Drive

MCAFSX

Hi-Z, Pull, Drive

GPIO12 (PN)

I/O

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

McACLK

Hi-Z, Pull, Drive

pVS(VSYNC)

Hi-Z, Pull, Drive

I2C_SCL

I/O (open drain)

Hi-Z, Pull, Drive

UART0_TX

GT_CCP03

Hi-Z, Pull, Drive

GPIO13 (PN)

I/O

Hi-Z, Pull, Drive

Hi-Z, Pull,

Drive

Hi-Z

I2C_SDA

I/O (open drain)

pHS(HSYNC)

UART0_RX

GT_CCP04

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CC3230S, CC3230SF

SWRS226 – FEBRUARY 2020

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