TSB41BA3FTPFPEP datasheet(34/73 Pages) TI

34 / 73 page

Table 12-4 shows the encoding for the request type.

Table 12-4. Request Type Encoding

LR1–LR3

NAME

DESCRIPTION

000

ImmReq

Immediate bus request. On detection of idle, the PHY takes control of the bus immediately without arbitration.

001

IsoReq

Isochronous bus request. On detection of idle, the PHY arbitrates for the bus without waiting for a subaction

gap.

010

PriReq

Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol.

011

FairReq

Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol.

100

RdReg

The PHY returns the specified register contents through a status transfer.

101

WrReg

Write to the specified register

110

AccelCtl

Enable or disable asynchronous arbitration acceleration

111

Reserved

For a bus request, the length of the LREQ bit stream is 7 or 8 bits as shown in Table 12-5.

Table 12-5. Bus Request

BIT(s)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

1–3

Request type

Indicates the type of bus request. See Table 12-4.

4–6

Request speed

Indicates the speed at which the PHY sends the data for this request. See Table 12-6 for the encoding of this

field.

Stop bit

Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit can be omitted.

Table 12-6 shows the 3-bit request speed field used in bus requests.

Table 12-6. Bus Request Speed Encoding

LR4–LR6

DATA RATE

000

S100

010

S200

100

S400

All Others

Invalid

Note

The TSB41BA3F-EP accepts a bus request with an invalid speed code and processes the bus request

normally. However, during packet transmission for such a request, the TSB41BA3F-EP ignores any

data presented by the LLC and transmits a null packet.

For a read register request, the length of the LREQ bit stream is 9 bits as shown in Table 12-7.

Table 12-7. Read Register Request

BIT(s)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1)

1–3

Request type

A 100 indicates this is a read register request.

4–7

Address

Identifies the address of the PHY register to be read

Stop bit

Indicates the end of the transfer (always 0)

For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 12-8.

TSB41BA3F-EP

SLLSFA1 – SEPTEMBER 2020

www.ti.com

Submit Document Feedback

Product Folder Links: TSB41BA3F-EP

TSB41BA3FTPFPEP Datasheet(PDF) 34 Page - Texas Instruments

TSB41BA3FTPFPEP Datasheet(HTML) 34 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL