TSB41BA3FTPFPEP datasheet(4/73 Pages) TI

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TERMINAL

I/O

DESCRIPTION

NAME

TYPE

PFP

NO.

BMODE

CMOS

Beta-mode input. This terminal determines the PHY-link interface connection protocol.

When logic-high (asserted), the PHY-link interface complies with the 1394b-2002 B PHY-

link interface. When logic-low (deasserted), the PHY-link interface complies with the legacy

1394a-2000 standard. When using an LLC such as the 1394b-2002 TSB82AF15-EP, this

terminal must be pulled high. When using an LLC such as the 1394a-2000 TSB12LV26,

this terminal must be tied low.

Note

NOTE: The PHY-link interface cannot be changed between the different

protocols during operation.

CPS

CMOS

Cable-power status input. This terminal is normally connected to cable power through a

400-kΩ resistor. This circuit drives an internal comparator that detects the presence of

cable power. This transition from cable power sensed to cable power not sensed can be

used to generate an interrupt to the LLC.

CTL0

CTL1

CMOS

I/O

Control I/Os. These bidirectional signals control communication between the TSB41BA3F-

EP and the LLC. Bus holders are built into these terminals.

D0–D7

CMOS

11, 12,

13, 15,

16, 17,

19, 20

I/O

Data I/Os. These are bidirectional data signals between the TSB82BA3 and the LLC. Bus

holders are built into these terminals.

If power management control (PMC) is selected using LCLK_PMC, then some of these

terminals can be used for PMC. See the LCLK_PMC terminal description for more

information.

DGND

Supply

4, 14,

38, 64,

72, 76

Digital circuit ground terminals. These terminals must be tied together to the low-

impedance circuit board ground plane.

DVDD-CORE

Supply

8, 37,

65, 71

–

Digital core circuit power terminals. A combination of high-frequency decoupling capacitors

near each terminal is suggested, such as paralleled 0.1 μF and

0.001 μF. An additional 1-μF capacitor is required for voltage regulation. These supply

terminals are separated from the DVDD-3.3, PLLVDD-CORE, PLLVDD-3.3, and AVDD

terminals internal to the device to provide noise isolation.

DVDD-3.3

Supply

6, 18,

69, 70

–

Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling

capacitors near each terminal is suggested, such as paralleled 0.1 μF and

0.001 μF. Lower-frequency 10-μF filtering capacitors are also recommended. The

DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board.

These supply terminals are separated from the PLLVDD-CORE, PLLVDD-3.3, DVDD-

CORE, and AVDD terminals internal to the device to provide noise isolation. The

PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc

impedance connection on the circuit board.

TSB41BA3F-EP

SLLSFA1 – SEPTEMBER 2020

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