TSB41BA3FTPFPEP datasheet(60/73 Pages) TI

60 / 73 page

• The LCLK_PMC input (terminal 7) must be tied directly to ground or through a pulldown resistor of ~1 kΩ or

less, unless the PMC mode is desired (see LCLK_PMC terminal description).

All other signals are connected to their counterparts on the 1394a link-layer controller. The PCLK output

corresponds to the SCLK input signal on most LLCs.

The 1394a-2000 Supplement includes enhancements to the Annex J interface that should be comprehended

when using the TSB41BA3F-EP with a 1394-1995 LLC device.

• A new LLC service request was added which allows the LLC to temporarily enable and disable asynchronous

arbitration accelerations. If the LLC does not implement this new service request, then the arbitration

enhancements must not be enabled (see the EAA bit in PHY register 5).

• The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was

added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not

support multispeed concatenation, then multispeed concatenation must not be enabled in the PHY (see the

EMC bit in PHY register 5).

• In order to accommodate the higher transmission speeds expected in future revisions of the standard,

1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus

request from 7 bits to 8 bits. The new speed codes were carefully selected so that new 1394a-2000 PHY and

LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use

the 2-bit speed codes. The TSB41BA3F-EP correctly interprets both 7-bit bus requests (with 2-bit speed

code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately

followed by another request (for example, a register read or write request), then the TSB41BA3F-EP correctly

interprets both requests. Although the TSB41BA3F-EP correctly interprets 8-bit bus requests, a request with

a speed code exceeding S400 while in 1394a-2000 PHY-link interface mode results in the TSB41BA3F-EP

transmitting a null packet (data prefix followed by data end, with no data in the packet).

13.2.6 Power-Up Reset

To ensure proper operation of the TSB41BA3F-EP, the RESET terminal must be asserted low for a minimum of

2 ms from the time that PHY power reaches the minimum required supply voltage and the input clock to the PHY

is valid. When using a passive capacitor on the RESET terminal to generate a power-on-reset signal, the

minimum reset time is ensured if the value of the capacitor satisfies the following equation (the value must be no

smaller than approximately 0.1 μF):

Cmin = 0.0077 × T + 0.085 + (external_oscillator_start-up_time × 0.05)

Where Cmin is the minimum capacitance on the RESET terminal in μF, T is the VDD ramp time, 10%–90%, in ms,

external_oscillator_start-up_time is the time in ms from application of power to the external oscillator until the

oscillator outputs a valid clock. If a crystal is used rather than an oscillator, then the external_oscillator_start-

up_time can be set to 0.

For example with a 2-ms power ramp time and a 2-ms oscillator start-up time:

Cmin = 0.0077 × 2 + 0.085 + (2 × 0.05) = 0.2 μF

It is appropriate to select the nearest standard value capacitor that exceeds this value, for example 0.22 μF.

Or with a 2-ms power ramp time and a 49.152-MHz fundamental crystal:

Cmin = 0.0077 × 2 + 0.085 + (0 × 0.05) = 0.1 μF

13.2.7 Crystal Selection

The TSB41BA3F-EP and other Texas Instruments PHY devices are designed to use an external 49.152-MHz

crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This

oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and

resynchronization of data at the S100 through S400 media data rates.

A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent

PHYs can therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must

TSB41BA3F-EP

SLLSFA1 – SEPTEMBER 2020

www.ti.com

Submit Document Feedback

Product Folder Links: TSB41BA3F-EP

TSB41BA3FTPFPEP Datasheet(PDF) 60 Page - Texas Instruments

TSB41BA3FTPFPEP Datasheet(HTML) 60 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL