TSB41BA3FTPFPEP datasheet(46/73 Pages) TI

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(the paged registers) depends on which of eight pages, numbered 0h through 7h, is currently selected. The

selected page is set in base register 7h. Note that while this register set is compatible with 1394a-2000 register

sets, some fields have been redefined, and this register set contains additional fields.

Table 13-1 shows the configuration of the base registers, and Table 13-2 gives the corresponding field

descriptions. The base register field definitions are unaffected by the selected page number.

A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is

read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.

Table 13-1. Base Register Configuration

Address

BIT POSITION

0000

Physical ID

CPS

0001

RHB

IBR

Gap_Count

0010

Extended (111b)

Num_Ports (0011b)

0011

PHY_Speed (111b)

SREN

Delay (1011b)

0100

LCtrl

Jitter (000b)

Pwr_Class

0101

WDIE

ISBR

CTOI

CPSI

STOI

PEI

EAA

EMC

0110

Max Legacy SPD

BLINK

Bridge

Rsvd

0111

Page_Select

Rsvd

Port_Select

Table 13-2. Base Register Field Descriptions

FIELD

SIZE

TYPE

DESCRIPTION

Physical ID

This field contains the physical address ID of this node determined during self-ID. The physical-ID is

invalid after a bus reset until the self-ID has completed as indicated by an unsolicited register 0 status

transfer from the PHY to the LLC.

Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1

during tree-ID if this node becomes root.

CPS

Cable-power status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally

tied to serial bus cable power through a 400-kΩ resistor. A 0 in this bit indicates that the cable-power

voltage has dropped below its threshold for ensured reliable operation.

RHB

Rd/Wr

Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB bit

is reset to 0 by a hardware reset and is unaffected by a bus reset. If two nodes on a single bus have their

root holdoff bit set, then the result is not defined. To prevent two nodes from having their root-holdoff bit

set, this bit must only be written using a PHY configuration packet.

IBR

Rd/Wr

Initiate bus reset. This bit instructs the PHY to initiate a long (166-μs) bus reset at the next opportunity.

Any receive or transmit operation in progress when this bit is set completes before the bus reset is

initiated. The IBR bit is reset to 0 after a hardware reset or a bus reset. Care must be exercised when

writing to this bit to not change the other bits in this register. It is recommended that whenever possible a

bus reset be initiated using the ISBR bit and not the IBR bit.

Gap_Count

Rd/Wr

Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. The

gap count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG

packet. The gap count is reset to 3Fh by hardware reset or after two consecutive bus resets without an

intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG

packet). It is strongly recommended that this field only be changed using PHY configuration

packets.

Extended

Extended register definition. For the TSB41BA3F-EP, this field is 111b, indicating that the extended

Num_Ports

Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41BA3F-

EP, this field is 3.

PHY_Speed

PHY speed capability. This field is no longer used. For the TSB41BA3F-EP PHY, this field is 111b. Speeds

for 1394b PHYs must be checked on a port-by-port basis.

SREN

Rd/Wr

Standby/restore enable. This bit when set to 1 enables the port to go into the standby reduced power

state when commanded by a Standby PHY command packet. This enable works for all ports of the local

device. Note the 1394b standard only allows leaf (one port connected) nodes to be placed into standby

mode.

TSB41BA3F-EP

SLLSFA1 – SEPTEMBER 2020

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