TSB41BA3FTPFPEP datasheet(6/73 Pages) TI

6 / 73 page

TERMINAL

I/O

DESCRIPTION

NAME

TYPE

PFP

NO.

CMOS

Power-down input. A high on this terminal turns off all internal circuitry. Asserting the PD

input high also activates an internal pulldown on the RESET terminal to force a reset of the

internal control logic.

PINT

CMOS

PHY interrupt. The PHY uses this output to serially transfer status and interrupt information

to the link when PHY-link interface is in the 1394b mode. A bus holder is built into this

terminal.

PLLGND

Supply

25, 28

–

PLL circuit ground terminals. These terminals must be tied together to the low-impedance

circuit board ground plane.

PLLVDD-CORE Supply

29, 30

–

PLL core circuit power terminals. A combination of high-frequency decoupling capacitors

near each terminal is suggested, such as paralleled 0.1 μF and

0.001 μF. An additional 1-μF capacitor is required for voltage regulation. The PLLVDD-

CORE terminals must be separate from the DVDD-CORE terminals. These supply

terminals are separated from the DVDD-CORE, DVDD-3.3, PLLVDD-3.3, and AVDD-3.3

terminals internal to the device to provide noise isolation.

PLLVDD-3.3

Supply

–

PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors

near the terminal are suggested, such as paralleled 0.1 μF and

0.001 μF. Lower frequency 10-μF filtering capacitors are also recommended. This supply

terminal is separated from the DVDD-CORE, DVDD-3.3, PLLVDD-CORE, and AVDD-3.3

terminals internal to the device to provide noise isolation. The DVDD-3.3 terminals must be

tied together at a low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3,

and DVDD-3.3 terminals must be tied together with a low dc impedance connection.

RESET

CMOS

Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup

resistor to VDD is provided so only an external delay capacitor is required for proper power-

up operation (see power-up reset in the Application Information section). The RESET

terminal also incorporates an internal pulldown which is activated when the PD input is

asserted high. This input is otherwise a standard logic input, and can also be driven by an

open-drain-type driver.

Bias

–

Current setting resistor terminals. These terminals are connected to a precision external

resistance to set the internal operating currents and cable driver output currents. A

resistance of 6.34 kΩ ±1% is required to meet the IEEE Std 1394-1995 output voltage

limits.

CMOS

Test control input. This input is used in the manufacturing test of the TSB41BA3F-EP. For

normal use, this terminal must be pulled low either through a 1-kΩ resistor to GND or

directly to GND.

ENHANCE_EN

CMOS

Enhancement Enable Formerly SLPEN Automotive sleep mode enable input. At power-on

reset, FPR, FRT and FTD register values are set by ENHANCE_EN. - When

ENHANCE_EN is low FPR, FRT and FTD enhancements are enabled. - When

ENHANCE_EN is high FPR, FRT and FTD enhancements are disabled. See Section

13.2.3.NOTE: SLPEN has not been used in most applications. In most applications pin 79

SLPEN was tied to ground (low). If the TSB41BA3F-EP device is used as a drop-in

replacement where pin 79 ENHANCE_EN is low, all three enhancements will be enabled

without any hardware or software changes. If automotive sleep mode is required, then it

would be required to use revision D or enable sleep mode through software programming

of page 0 registers.

CMOS

Test control input. This input is used in the manufacturing test of the TSB41BA3F-EP. For

normal use this terminal must be pulled low either through a 1-kΩ resistor to GND or

directly to GND.

S2_PC0

S1_PC1

S0_PC2

CMOS

Port mode selection terminals 2-0 and power-class programming. On hardware reset, this

terminal when used with the other five selection terminals allows the user to select the

speed and mode of the ports. See Table 5-1. Depending on the selection, these inputs can

set the default value of the power class indicated during self-ID.

Programming is done by tying the terminals high through a 1-kΩ resistor or by tying directly

to ground through a 1-kΩ resistor. Bus holders are built into these terminals.

CMOS

Port mode selection terminal 3. On hardware reset, this terminal when used with the other

five selection terminals allows the user to select the speed and mode of the ports. See

Table 5-1. Programming is done by tying the terminals high through a 1-kΩ or smaller

resistor or by tying directly to ground through a 1-kΩ or smaller resistor. A bus holder is built

into this terminal.

TSB41BA3F-EP

SLLSFA1 – SEPTEMBER 2020

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