TSB41BA3FTPFPEP datasheet(7/73 Pages) TI

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TERMINAL

I/O

DESCRIPTION

NAME

TYPE

PFP

NO.

CMOS

Port mode selection terminal 4. On hardware reset, this terminal when used with the other

five selection terminals allows the user to select the speed and mode of the ports. See

Table 5-1. Programming is done by tying the terminals high through a 1-kΩ or smaller

resistor or by tying directly to ground through a 1-kΩ or smaller resistor. A bus holder is built

into this terminal.

S5_LKON

CMOS

I/O

Port mode selection terminal 5 and link-on output. This terminal can be connected to the

link-on input terminal of the LLC through a 1-kΩ resistor if the link-on input is available on

the link layer.

On hardware reset this terminal, when used with the other Port Speed/Mode Selection

terminals, allows the user to select whether ports act like a 1394b bilingual port (terminal at

logic 0) or as a 1394a-2000-only port (terminal 1394b bilingual mode or high through a 1-

kΩ or less resistor to enable 1394b bilingual mode or high through a 1-kΩ or less resistor to

enable 1394a-2000-only mode. A bus holder is built into this terminal. See Table 5-1. A bus

holder is built into this terminal.

After hardware reset, this terminal is the link-on output, which notifies the LLC or other

power-up logic to power up and become active. The link-on output is a square wave signal

with a period of approximately 163 ns (8 PCLK cycles) when active. The link-on output is

otherwise driven low, except during hardware reset when it is high-impedance.

The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit

cleared) and when one of the following occurs:

1. The PHY receives a link-on PHY packet addressed to this node.

2. The PEI (port-event interrupt) register bit is 1.

3. Any of the CTOI (configuration-timeout interrupt),

CPSI (cable-power-status interrupt), or STOI (state-time-out interrupt) register bits is 1

and the RPIE (resuming-port interrupt enable) register bit is also 1.

4. The PHY is power-cycled and the power class is 0 through 4.

Once activated, the link-on output is active until the LLC becomes active (both the LPS

input active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-

reset occurs unless the link-on output is otherwise active because one of the interrupt bits

is set (that is, the link-on output is active due solely to the reception of a link-on PHY

packet).

In the case of power-cycling the PHY, the LKON signal must stop after 167 µs if the

preceding conditions have not been met.

Note

NOTE: If an interrupt condition exists which otherwise would cause the link-on

output to be activated if the LLC were inactive, then the link-on output is

activated when the LLC subsequently becomes inactive.

TESTM

CMOS

Test control input. This input is used in the manufacturing test of the TSB41BA3F-EP. For

normal use this terminal must be pulled high through a 1-kΩ resistor to VDD.

TPA0–

TPA0+

TPB0–

TPB0+

Cable

I/O

Port-0 twisted-pair differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. Request the S800 1394b layout

recommendations document from your Texas Instruments representative.

TPA1–

TPA1+

TPB1–

TPB1+

Cable

I/O

Port-1 twisted-pair differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. Request the S800 1394b layout

recommendations document from your Texas Instruments representative.

TPA2–

TPA2+

TPB2–

TPB2+

Cable

I/O

Port-2 twisted-pair differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. Request the S800 1394b layout

recommendations document from your Texas Instruments representative.

www.ti.com

TSB41BA3F-EP

SLLSFA1 – SEPTEMBER 2020

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