UPD17P136ACT datasheet(120/292 Pages) NEC

120 / 292 page

CHAPTER 12

PORTS

12.1 PORT 0A (P0A0, P0A1, P0A2, P0A3)

Port 0A is a 4-bit input/output port with an output latch. It is mapped into address 70H of BANK0 in data memory.

The output format is CMOS push-pull output.

Input or output can be specified in 4-bit units. Input/output is specified by P0AGIO (bit 0 at address 2CH) in the

When P0AGIO is 0, all pins of port 0A are used as input port. If a read instruction is executed for the port register,

pin statuses are read.

When P0AGIO is 1, all pins of port 0A are used as output port and the contents written in the output latch are output

to pins. If a read instruction is executed when pins are output ports, the contents of the output latch, rather than pin

statuses, are fetched.

Port 0A contains a software-controlled pull-up resistor. P0AGPU (bit 0 at address 0CH) of the register file is used

to determine whether port 0A contains the pull-up resistor. When P0AGPU is 1, all 4-bit pins are pulled up. If P0AGPU

is 0, the pull-up resistor is not contained.

At reset, P0AGIO and P0AGPU are set to 0 and all P0A pins become input ports without a pull-up resistor. The

contents of the port output latch are 0.

Table 12-1. Writing into and Reading from the Port Register (0.70H)

BANK0 70H

Read

P0A pin status

P0A latch contents

Write

Possible

Write to the P0A latch

Input

Output

Pin input/output

P0AGIO

RF: 2CH, bit 0

101

UPD17P136ACT Datasheet(PDF) 120 Page - NEC