UPD17P136ACT datasheet(121/292 Pages) NEC

121 / 292 page

CHAPTER 12 PORTS

102

12.2 PORT 0B (P0B0, P0B1, P0B2, P0B3)

Port 0B is a 4-bit input/output port with an output latch. It is mapped into address 71H of BANK0 in data memory.

The output format is CMOS push-pull output.

Input or output can be specified in 4-bit units. Input/ output is specified by P0BGIO (bit 1 at address 2CH) in the

When P0BGIO is 0, all pins of port 0B are used as input ports. If a read instruction is executed for the port register,

pin statuses are read.

When P0BGIO is 1, all pins of port 0B are used as output ports. The contents written in the output latch are output

to pins. If a read instruction is executed when pins are used as output ports, the contents of the output latch, rather

than pin statuses, are fetched.

Port 0B contains a software-controlled pull-up resistor. P0BGPU (bit 1 at address 0CH) is used to determine

whether or not port 0B contains a pull-up resistor. When P0BGPU is 1, all 4-bit pins are pulled up. When P0BGPU

is 0, a pull-up resistor is not contained.

At reset, P0BGIO and P0BGPU are 0 and all P0B pins are input ports without a pull-up resistor. The value of the

port 0B output latch is 0.

Table 12-2. Writing into and Reading from the Port Register (0.71H)

BANK0 71H

Read

P0B pin status

P0B latch contents

Input

Output

Pin input/output

P0BGIO

RF: 2CH, bit 1

Write

Possible

Write to the P0B latch

UPD17P136ACT Datasheet(PDF) 121 Page - NEC