UPD17P136ACT datasheet(124/292 Pages) NEC

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CHAPTER 12 PORTS

105

Port mode

Input port

Output port

TM0OUT

SCK

Contents read from the port register (0.73H)

Pin status

Output latch contents

Pin status

Not defined

Output latch contents

An internal clock is selected as a shift clock.

An external clock is selected as a shift clock.

BANK1 70H

Pin input/output

(n = 0 to 3)

P1AGIOn

RF: 2CH, bit 2

Input

Output

Write

Possible

Write to the P1A latch

Read

P1A pin status

P1A latch contents

Table 12-5. Contents Read from the Port Register (0.73H)

Caution Using the serial interface causes the output latch for the P0D1/SO pin to be affected by the

contents of the SIOSFR (shift register). So, reset the output latch before using the pin as output

port.

12.5

PORT 1A (P1A0, P1A1, P1A2, P1A3)

Port 1A is a 4-bit input/output port with an output latch. It is mapped into address 70H of BANK1 in data memory.

The output format is N-ch open-drain output. The mask option can be used to specify that a pin contain a pull-up

resistor in 1-bit unit.

Input or output can be specified in 4-bit units. Input/output is specified by P1AGIO (bit 2 at address 2CH) in the

When P1AGIO is 0, each pin of port 1A is used as input port. If a read instruction is executed for the port register,

pin statuses are read. When P1AGIO is 1, each pin of port 1A is used as output port and the contents written in the

output latch are output to pins. If a read instruction is executed when pins are output ports, the contents of the output

latch, rather than pin statuses, are fetched.

At reset, P1AGIO is set to 0 and all P1A pins become input ports. The contents of the port output latch are

Table 12-6. Writing into and Reading from the Port Register (1.70H)

12.6 PORT 1B (P1B0)

Port 1B is a 1-bit input-dedicated port. It is mapped into address 71H of BANK1 in data memory. The mask option

can be used to specify that pull-up resistors be contained in P1B0 pins.

Port 1B is the input-dedicated port. At reading, only the least significant bit is valid and a value is read into it. At

writing, no value changes. Value 0 is always read into the high-order 3 bits of the port register.

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