UPD17P136ACT datasheet(139/292 Pages) NEC

139 / 292 page

CHAPTER 13 PERIPHERAL HARDWARE

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(b) If counting is started when count pulse is low (error: –1 to –1.5 count)

In this example, the coincidence signal must be output each time the count value has reached 2. However,

the first coincidence signal is output when the count value is 1.5 at maximum or 0.5 at minimum (error: –0.5

to –1.5 count).

The above error also occurs during oscillation stabilization wait time because the timer is also used to generate

the oscillation stabilization wait time.

101

Count register

Count pulse

Coincidence signal output

Count starts (TMnEN = 1

← 0)

2 counts

Coincidence signal output

1 to 1.5 count

(2) Error when counting is started from count stop status (maximum error: –1.5 count)

The count register of the 8-bit timer is cleared to 0 by setting the TMnRES flag to 1. However, the divider circuit

that generates a count pulse from the system clock is not reset.

If the TMnEN flag is set to 1 and counting is started from the count stop status, the timing of the first counting

differs as follows depending on whether the count pulse starts with a low level or a high level.

If count pulse starts with high level: First count at the next rising

If count pulse starts with low level: First count on starting of counting

Therefore, an error of –0.5 to 1.5 count occurs until the coincidence signal is output for the first time after

counting has been started. An example of counting where the modulo register is set to 1 is shown below.

Figure 13-7. Error When Counting Is Started from Count Stop Status

(a) If counting is started when count pulse is high (error: –0.5 to –1 count)

Count register

Count pulse

Coincidence signal output

Count starts (TMnEN = 1

← 0)

2 counts

Coincidence signal output

0.5 to 1 count

UPD17P136ACT Datasheet(PDF) 139 Page - NEC