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UPD17P136ACT Datasheet(PDF) 150 Page - NEC |
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UPD17P136ACT Datasheet(HTML) 150 Page - NEC |
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150 / 292 page  CHAPTER 13 PERIPHERAL HARDWARE 131 Figure 13-14. A/D Converter Control Register (2/2) Note With the µPD17134A subseries, ADCR is reset to 0 if the ADCSTRT flag is set, regardless of the A/D conversion mode. In the single mode, start conversion by writing a value to ADCR. 0 0 ADCSTRT Start of A/D operation 1 RF: 20 H Read = R, write = W Bit 3 Bit 2 Bit 1 Bit 0 R/W 00 0 Read/write Initial value when reset ADCSTRT 00 0 Initial status or during A/D conversion. Cleared to 0 automatically after A/D conversion (successive or single modeNote) starts. 0 ADCCH1 Analog input channel selection ADC0 is selected. 0 ADC1 is selected. RF: 22H Read = R, write = W 0 Bit 3 Bit 2 Bit 1 Bit 0 R/W ADCCH3 ADCCH2 Read/write Initial value when reset ADCCH0 00 0 ADCCH1 0 1 ADCCH0 1 1 0 1 ADC2 is selected. ADC3 is selected. Fixed to 0. (Dummy flag) |
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