F4481 Datasheet

© 2020 Renesas Electronics Corporation

33

December 15, 2020

Programming

The F4481 employs a variety of programming options which can be used to control the on-chip attenuators and band-select functions. The

following sections provide specific details on each unique programming mode.

Serial Programming

The F4481 includes a SPI interface which is primarily used to program the device’s on-chip attenuators.

Device Register Maps

Each channel of the VGA uses an 8-bit addressing word followed by an 8-bit data word to execute the attenuation level commands. Figure 64

shows the various bit assignments for each channel register.

Figure 64. Register Bit Map for Each Channel

Address Word A7 – A0

Data Word D7 – D0

D6

D5

D1

D4

D2

D3

16 dB

RSV

LSB

RSV

RSV

RSV RSV

8 dB

4 dB

2 dB

1 dB

0.5 dB

MSB

D7

CH

SEL

CH

SEL

A6

A7

A5

A1

A4

A2

A3

A0

D0

LSB

MSB

RSV

CH

SEL

RSV

The register address word (Bits A7-A0) includes five reserve bits (A7-A3) followed by three channel addressing bits (A2-A0). The channel select

truth table is provided in Table 8.

Table 8.

Channel Select Truth Table

Channel Select

Reserve

Address Bits

A7

A6

A5

A4

A3

A2

A1

A0

Channel A

X

X

X

X

X

0

0

0

Channel B

X

X

X

X

X

0

0

1

Channel C

X

X

X

X

X

0

1

0

Channel D

X

X

X

X

X

0

1

1

Channel A and B

(Simultaneous Programming)

X

X

X

X

X

1

0

X

Channel C and D

(Simultaneous Programming)

X

X

X

X

X

1

1

X

Note that address bit A2 is used to select either individual channel programming (logic LOW) or dual channel programming (logic HIGH).

Simultaneous programming of channels A and B is achieved when setting bit A2 to a logic HIGH and A1 a logic LOW. Simultaneous

programming of channels C and D occurs when bits A2 and A1 are both logic HIGHs.

Table 9 represents the truth table for the attenuator control bits. A full scale DSA setting of 000000 drives the channel DSA into its minimum

attenuation state. Conversely, a setting of 111111 drives the channel DSA into its maximum attenuation state. Note that D5 is defined as the

Most Significant Bit (MSB) for the attenuator control function within each respective channel.