F4481 Datasheet

© 2020 Renesas Electronics Corporation

35

December 15, 2020

Timing Associated with Programming the Serial Registers

To program each channel, the Address Word and Data Word must be clocked in sequentially with the Most Significant Bit (MSB) first (for details,

see Figure 66).

Figure 66. Timing Diagram Associated with Programming the Serial Register

Address Word A7 – A0

Data Word D7 – D0

D6

D5

D1

D4

D2

D3

16dB

CLK

DATA

Data Word

Latched into

Register

LSB

0

0

0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

8dB

4dB

2dB

1dB

0.5dB

MSB

CSb

Increasing Time

D0

D7

CH

SEL

CH

SEL

A6

A7

A5

A1

A4

A2

A3

A0

LSB

MSB

CH

SEL

0

0

0

SPI Timing Intervals

Figure 67 shows the relevant SPI timing intervals that are specified in Table 10.

Note – The F4481 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device is not being programmed.

Figure 67. Serial Register Timing Diagram

MSB

LSB

Time

CLK

DATA

CSb