F4481 Datasheet

© 2020 Renesas Electronics Corporation

34

December 15, 2020

Table 9.

DVGA Attenuation Word Truth Table

Attenuation

Setting

Reserve

Control Bits

D7

D6

D5

D4

D3

D2

D1

D0

0.0 dB

X

X

0

0

0

0

0

0

0.5 dB

X

X

0

0

0

0

0

1

1.0 dB

X

X

0

0

0

0

1

0

2.0 dB

X

X

0

0

0

1

0

0

4.0 dB

X

X

0

0

1

0

0

0

8.0 dB

X

X

0

1

0

0

0

0

16.0 dB

X

X

1

0

0

0

0

0

31.5 dB

X

X

1

1

1

1

1

1

It should also be noted that the listing above represents an abbreviated version of the complete 6-bit attenuator control truth table. Any attenuator

combination of 0.5dB, 1dB, 2dB, 4dB, 8dB, and 16dB can be achieved by simply assigning a logic HIGH in the respective control bit. For

instance, to achieve an attenuation setting of 21.5dB within a given channel, assign a logic HIGH to bits D0, D1, D3, and D5 while assigning a

logic LOW to bits D2 and D4. Doing so selects a combination of 0.5dB (D0) + 1dB (D1) + 4dB (D3) + 16dB (D5) = 21.5dB. Setting all of the

control bits to logic HIGH will step in all of the attenuator stages.

Serial Mode Default Condition

When the device is first powered on, each channel’s DSA will default to its Maximum Attenuation setting as shown below in Figure 65. These

Figure 65. Serial Mode Default Condition upon Initial Power-Up

D6

D7

D5

D1

D4

D2

D3

D0

All Channels

Set With

31.5dB Attenuation

Channel B D7 – D0 Register Defaults

D6

D7

D5

D1

D4

D2

D3

D0

Channel A D7 – D0 Register Defaults

Channel C D7 – D0 Register Defaults

D6

D7

D5

D1

D4

D2

D3

D0

Channel D D7 – D0 Register Defaults

D6

D7

D5

D1

D4

D2

D3

D0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1