EM4095

Copyright

 2002, EM Microelectronic-Marin SA

7

www.emmicroelectronic.com

Signal RDY/CLK

This signal provides the external microprocessor with

clock signal which is synchronous with the signal on ANT1

and with information about EM4095 internal state. Clock

signal synchronous with ANT1 indicates that PLL is in lock

and that Reception chain operation point is set. When

SHD is high RDY/CLK pin is forced low. After high to low

transition on SHD the PLL starts-up, and the reception

reception chain operation point has been established. At

this moment the same signal which is being transmitted to

ANT1 is also put to RDY/CLK pin indicating to

microprocessor that it can start observing signal on

DEMOD_OUT and giving at the same time reference

clock signal. Clock on RDY/CLK pin is continuous, it is

also present during time the ANT drivers are OFF due to

low transition on SHD pin RDY/CLK pin is pulled down by

100 k

Ω pull down resistor. The reason for this is in

additional functionality of RDY/CLK pin in case of AM

modulation with index which is lower then 100%. In that

case it is used as auxiliary driver which maintains lower

amplitude on coil during modulation. (see also Typical

Operating Configuration)

Remark: Please refer to AN4095 for external components

calculation and limits.

Typical Operating Configuration

Read Only Mode

µP

+5V

L

A

C

DV1

C

DV2

C

RES

P4095

2

3

4

5

6

7

8

1

15

14

13

12

11

10

9

16

+5V

RDY/CLK

C

DEC

C

AGND

MOD

DEMOD_OUT

SHD

C

DC2

C

FCAP

Fig. 6

Read/Write mode (Low Q factor antenna)

µP

+5V

L

A

C

DV1

C

DV2

C

RES

C

DEC

C

AGND

P4095

2

3

4

5

6

7

8

1

15

14

13

12

11

10

9

16

+5V

MOD

DEMOD_OUT

SHD

C

DC2

C

FCAP

RDY/CLK

Fig. 7

Read/Write mode (High Q factor antenna)

µP

+5V

L

A

C

DV1

C

DV2

C

RES

P4095

2

3

4

5

6

7

8

1

15

14

13

12

11

10

9

16

+5V

RDY/CLK

R

SER

C

DEC

C

AGND

MOD

DEMOD_OUT

SHD

C

DC2

C

FCAP

Fig. 8

Read/Write mode (AM modulation)

µP

+5V

L

A

C

DV1

C

DV2

C

RES

P4095

2

3

4

5

6

7

8

1

15

14

13

12

11

10

9

16

+5V

RDY/CLK

R

AM

C

DEC

C

AGND

MOD

DEMOD_OUT

SHD

C

DC2

C

FCAP

Fig. 9

Figure 6 presents EM4095 used in Read Only mode. Pin

MOD is not used. It is recommended to connect it to VSS.

Figure 7 presents typical R/W configuration for OOK

communication protocol reader to transponder (eg.

EM4150). It is recommended to be used with low Q factor

antennas (up to 15).

When the antenna quality is high using configuration of

figure 6 or 7 the voltage on antenna can arrive in the

range of few hundred volts and antenna peak current may

exceed its maximum value. In such a case the capacitive

divider ratio has to be high thus limiting the sensitivity. For

such case it is better to reduce antenna circuit quality by

adding serial resistor. In this way the antenna current is

lower and thus power dissipation of IC is reduced with

practically the same performance (Fig. 8).

In the case AM modulation communication protocol

reader to transponder (eg. EM4069) is needed a single

ended configuration has to be used (figure 9). When pin

MOD is pulled high driver on ANT1 is put in three state,

driver RDY/CLK continues driving thus maintaining lower

antenna current. Modulation index is adjusted by resitor

active only after the demodulation chain operating point is

set.

Before it is pulled down by high impedance pull down

resistor (100 k

Ω) in order not to load ANT1 output. In the

case of AM modulation configuration the total antenna

current change at the moment RDY/CLK pin becomes

active, so external microprocessor has to wait another

EM4095

EM4095

EM4095

EM4095