EM4095 datasheet(8/10 Pages) EMMICRO

8 / 10 page

EM4095

 2002, EM Microelectronic-Marin SA

www.emmicroelectronic.com

Read Only mode with external peak detector

µP

+5V

DV1

DV2

RES

P4095

+5V

RDY/CLK

DEC

AGND

MOD

DEMOD_OUT

SHD

DC2

FCAP

Fig. 10

Read/Write mode with external peak detector

µP

+5V

DV1

DV2

RES

DEC

P4095

+5V

RDY/CLK

AGND

MOD

DEMOD_OUT

SHD

DC2

FCAP

Fig. 11

As mentioned above for high Q antennas the voltage on

antenna is high and read sensitivity is limited by

demodulator sensitivity due to capacitive divider. Read

sensitivity (and thus reading range) can be increased by

using external envelope detector circuit. Input is taken on

antenna high voltage side output is directly fed to

CDEC_IN pin. However, the capacitor divider is still

needed for PLL locking. Such configuration is shown in

figure 5, the envelope detector is formed by three

components: D1, R1 and C1.

The configuration presented in figure 9 may also be used

for read write applications but it has a drawback in the

case

fast

recovery

reading

needed

after

communication reader to transponder is finished. The

reason is in fact that DC voltage after diode D1 is lost

during modulation and it takes very long time before it is

established again.

Figure 10 presents a solution to that problem. A high

voltage NMOS transistor blocks the discharge path during

modulation, so operating point is preserved. The signal

controlling NMOS gate has to be put low synchronously

with signal MOD, but it can be put high only after the

amplitude on antenna has recovered after modulation.

PCB Layout

Refer to "EM4095 Application Note" (App. Note 404)

EM4095

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