ADC3583 datasheet(42/75 Pages) TI

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8.5 Programming

The device is primarily configured and controlled using the serial programming interface (SPI) however it can

operate in a default configuration without requiring the SPI interface. Furthermore the power down function as

well as internal/external reference configuration is possible via pin control (PDN/SYNC and REFBUF pin).

Note

The power down command (via PIN or SPI) only goes in effect with the ADC sampling clock present.

8.5.1 Configuration using PINs only

The ADC voltage reference can be selected using the REFBUF pin. Even though there is an internal 100 kΩ

pull-up resistor to AVDD, the REFBUF pin should be set to a voltage externally and not left floating.

When using a voltage divider to set the REFBUF voltage (R1 and R2 in Figure 8-41), resistor values < 5 kΩ

should be used.

100 k

REFBUF

AVDD

Figure 8-41. Configuration of external voltage on REFBUF pin

Table 8-10. REFBUF voltage levels control voltage reference selection

REFBUF VOLTAGE

VOLTAGE REFERENCE OPTION

CLOCKING OPTION

> 1.7 V (Default)

External reference

Differential clock input

1.2 V (1.15-1.25V)

External 1.2V input on REFBUF pin using internal gain buffer

Differential clock input

0.5 - 0.7V

Internal reference

Differential clock input

< 0.1V

Internal reference

Single ended clock input

8.5.2 Configuration using the SPI interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting

bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when

SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low.

When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples

of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 12 MHz

down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

8.5.2.1 Register Write

The internal registers can be programmed following these steps:

1. Drive the SEN pin low

2. Set the R/W bit to 0 (bit A15 of the 16-bit address) and bits A[14:12] in address field to 0.

3. Initiate a serial interface cycle by specifying the address of the register (A[11:0]) whose content is written and

4. Write the 8-bit data that are latched in on the SCLK rising edges

Figure 8-42 shows the timing requirements for the serial register write operation.

ADC3583

SBAS873 – FEBRUARY 2021

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