PD69201 datasheet(3/29 Pages) MICROCHIP

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Functional Descriptions

The PD69201 device has two major sections: a digital section that controls and monitors the logical PoE functions

(state machines, timings, and so on) and an analog section that performs the front-end analog PoE functionality.

The following illustration shows the internal functional blocks of the PD69201 device.

Figure 1-1. PD69201 Internal Block Diagram

Analog

Digital

ADC I/F

AIR (Analog

Interface)

VCM

X FSM

CRG

(CPU/Control

Registers)

Addr

Decoder

I2C Client

MCM

ALU

x / + –

Startup

Power

Calibration

Management Block

Detection

FSM

Startup

FSM

Ongoing

Logic

LC Logic

Error

MCM

Logic

ALU

Res Det

Class

Startup

RTP

PMU

(PoE Macro Unit)

LED

Control

Clock

and

Reset

Logic

Voltage Register

5 V

POR

CLK

A/D

Port Control Circuity

Analog

Measurement

Thermal

Protection

Voltage Generator for

Line Detection and

Classification

Controlled

Reference

Current Limiter

Sense Resistor

Power

MOSFET

clk_d

POR

EPAD

IREF

VPORT_NEG

Disable_port

VMAIN

DRV_VAUX5

I2C_SCL

I2C_SDA

SCL

SDA

1.1

I2C Communication

The PD69201 can be controlled via I2C bus, based on registers access. There are two I2C addresses that can be set

(0x20 or 0x21). I2C address is set by pin 8.

1.1.1

Features

• I2C Client mode only.

• Data rate: 0 kbps–100 kbps

• Broadcast address: 0x00

• Watchdog reset. Resets the block if I2C input clock halts for 0.5 s during a transaction.

• Host does not need to support I2C clock stretching.

PD69201

Functional Descriptions

Datasheet

DS00003454D-page 3

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