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LTC7802 Datasheet(PDF) 28 Page - Analog Devices

Part # LTC7802
Description  40V Low IQ, 3MHz Dual, 2-Phase Synchronous Step-Down Controller with Spread Spectrum
PDF  34 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTC7802 Datasheet(HTML) 28 Page - Analog Devices

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LTC7802-3.3
28
Rev. 0
For more information www.analog.com
3. Verify that the minimum on-time of 40ns is not violated.
The minimum on-time occurs at VIN(MAX):
tON(MIN) =
VOUT
VIN(MAX)(fSW)
= 150ns
This is more than sufficient to satisfy the minimum on
time requirement. If the minimum on time is violated,
the LTC7802-3.3 skips pulses at high input voltage,
resulting in lower frequency operation and higher
inductor current ripple than desired. If undesirable, this
behavior can be avoided by decreasing the frequency
(with the inductor value accordingly adjusted) to avoid
operation near the minimum on-time.
4. Select the RSENSE resistor value. The peak inductor
current is the maximum DC output current plus half of
the inductor ripple current. Or 20A • (1+0.30/2) = 23A
in this case. The RSENSE resistor value can then be cal-
culated based on the minimum value for the maximum
current sense threshold (45mV):
RSENSE �
45mV
23A
� 2m�
To allow for additional margin, a lower value RSENSE
may be used (for example, 1.8mΩ); however, be sure
that the inductor saturation current has sufficient mar-
gin above VSENSE(MAX)/RSENSE, where the maximum
value of 55mV is used for VSENSE(MAX).
For this low inductor value and high current applica-
tion, an RC filter into the SENSE pins should be used
to compensate for the parasitic inductance (ESL) of the
sense resistor. Assuming an RSENSE geometry of 1225
with a parasitic inductance of 0.2nH, the RC filter time
constant should be RC = ESL/RSENSE = 0.2nH/2mΩ =
100ns, which may be implemented with 100Ω resis-
tor in series with the SENSE+ pin and 1nF capacitor
between SENSE+ and SENSE–.
5. Select the feedback resistors. If very light load effi-
ciency is required, high value feedback resistors may
be used to minimize the current due to the feedback
divider. However, in most applications a feedback
divider current in the range of 10μA to 100μA or more
is acceptable. For a 50μA feedback divider current,
RA = 0.8V/50μA = 16kΩ. RB can then be calculated
as RB = RA(3.3V/0.8V – 1) = 50kΩ. For channel 1, the
feedback resistor network is implemented internally.
Directly connect the VOUT1 pin to the output.
6. Select the MOSFETs. The best way to evaluate MOSFET
performance in a particular application is to build and
test the circuit on the bench, facilitated by an LTC7802-
3.3 demo board. However, an educated guess about
the application is helpful to initially select MOSFETs.
Since this is a high current, low voltage application, I2R
losses will likely dominate over transition losses for the
top MOSFET. Therefore, choose a MOSFET with lower
RDS(ON) as opposed to lower gate charge to minimize
the combined loss terms. The bottom MOSFET does
not experience transition losses, and its power loss is
generally dominated by I2R losses. For this reason,
the bottom MOSFET is typically chosen to be of lower
RDS(ON) and subsequently higher gate charge than the
top MOSFET.
Due to the high current in this application, two
MOSFETs may needed in parallel to more evenly bal-
ance the dissipated power and to lower the RDS(ON). Be
sure to select logic-level threshold MOSFETs, since the
gate drive voltage is limited to 5.1V (INTVCC). Minimize
the inductance of the TG and BG gate drive traces and
their respective return paths to the controller IC (SW
and GND) by using wide traces and multiple parallel
vias.
7. Select the input and output capacitors. CIN is chosen
for an RMS current rating of at least 10A (IOUT/2, with
margin) at temperature assuming only this channel
is on. COUT is chosen with an ESR of 3mΩ for low
output ripple. Multiple capacitors connected in parallel
may be required to reduce the ESR to this level. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due
to ESR is approximately:
VORIPPLE = ESR • ΔIL = 3mΩ • 6A = 18mVP-P
On the 3.3V output, this is equal to 0.55% of peak to
peak voltage ripple.
APPLICATIONS INFORMATION



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