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AD9988 Datasheet(PDF) 18 Page - Analog Devices |
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AD9988 Datasheet(HTML) 18 Page - Analog Devices |
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18 / 40 page  Data Sheet AD9988 SPECIFICATIONS analog.com Rev. 0 | 18 of 40 Table 17. 3 GSPS 4 GSPS Parameter Min Typ Max Min Typ Max Unit fIN1 = 1775 MHz, fIN2 = 1825 MHz −81 −84 dBFS fIN1 = 2675 MHz, fIN2 = 2725 MHz −77 −78 dBFS fIN1 = 3575 MHz, fIN2 = 3625 MHz −73 −74 dBFS fIN1 = 5375 MHz, fIN2 = 5425 MHz −66 −66 dBFS ANALOG BANDWIDTH4 7.5 7.5 GHz 1 Noise density is measured at 250 MHz input frequency at −30 dBFS, where timing jitter does not degrade noise floor. 2 Noise figure is based on a nominal full-scale input power of 4.5 dBm with an input span of 1.4 V p-p and RIN = 100 Ω. 3 With background interleaving calibration converged. 4 Analog input bandwidth is the bandwidth of operation in which the full-scale input frequency response rolls off by −3 dB based on a de-embedded model of the ADC extracted from the measured frequency response on evaluation board. This bandwidth requires optimized matching network to achieve this upper bandwidth. TIMING SPECIFICATIONS For the minimum and maximum values, TJ = −40°C to +120°C and ±5% of nominal supply, unless otherwise noted. Table 18. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SERIAL PORT INTERFACE (SPI) WRITE OPERATION Maximum SCLK Clock Rate fSCLK, 1/tSCLK 33 MHz SCLK Clock High tPWH SCLK = 33 MHz 8 ns SCLK Clock Low tPWL SCLK = 33 MHz 8 ns SDIO to SCLK Setup Time tDS 4 ns SCLK to SDIO Hold Time tDH 4 ns CSB to SCLK Setup Time tS 4 ns CLK to CSB Hold Time tH 4 ns SPI READ OPERATION LSB First Data Format Maximum SCLK Clock Rate fSCLK, 1/tSCLK 33 MHz SCLK Clock High tPWH 8 ns SCLK Clock Low tPWL 8 ns MSB First Data Format Maximum SCLK Clock Rate fSCLK, 1/tSCLK 15 MHz SCLK Clock High tPWH 30 ns SCLK Clock Low tPWL 30 ns SDIO to SCLK Setup Time tDS 4 ns SCLK to SDIO Hold Time tDH 4 ns CSB to SCLK Setup Time tS 4 ns SCLK to SDIO Data Valid Time tDV 20 ns SCLK to SDO Data Valid Time tDV_SDO 20 ns CSB to SDIO Output Valid to High-Z tZ 20 ns CSB to SDO Output Valid to High-Z tZ_SDO 20 ns RESETB Minimum hold time to trigger a device reset 40 ns Timing Diagrams |
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