AD9988 datasheet(23/40 Pages) AD

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Data Sheet

AD9988

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 23 of 40

Table 21. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

G10

TMU_REFP

Output

TMU ADC Positive Reference. Connect this pin to DVDD1P8.

Analog Inputs

A6, A5

ADC0P, ADC0N

Input

ADC0 Differential Inputs with Internal 100 Ω Differential

Resistor. Leave these pins floating if unused.

V6, V5

ADC1P, ADC1N

Input

ADC1 Differential Inputs with Internal 100 Ω Differential

Resistor. Leave these pins floating if unused.

A10, A9

ADC2P, ADC2N

Input

ADC2 Differential Inputs with Internal 100 Ω Differential

Resistor. Leave these pins floating if unused.

V10, V9

ADC3P, ADC3N

Input

ADC3 Differential Inputs with Internal 100 Ω Differential

Resistor. Leave these pins floating if unused.

VCO_FINE

Input

On-Chip Device Clock Multiplier and PLL Fine Loop Filter

Input. If the PLL is not in use, leave this pin floating and

disable the PLL via the control registers.

VCO_COARSE

Input

On-Chip Device Clock Multiplier and PLL Coarse Loop Filter

Input. If the PLL is not in use, leave this pin floating and

disable the PLL via the control registers.

VCO_VCM

Input

On-Chip Device Clock Multiplier and VCO Common-Mode

Input. If the PLL is not in use, leave this pin floating and

disable the PLL via the control registers.

N9, N10

TDP, TDN

Input

Anode and Cathode of Temperature Diodes. This feature is not

supported. Tie TDP and TDN to GND.

J1, K1

CLKINP, CLKINN

Input

Differential Clock Inputs with Nominal 100 Ω Termination.

These self biased inputs require ac coupling. When the on-

chip clock multiplier PLL is enabled, this input is the reference

clock input. If the PLL is disabled, an RF clock equal to the

DAC output sample rate is required.

CMOS Inputs and Outputs1

G13

CSB

Input

Serial Port Enable Input. Active low.

H13

SCLK

Input

Serial Plot Clock Input.

F13

SDIO

Input/output

Serial Port Bidirectional Data Input/Output.

J13

SDO

Output

Serial Port Data Output.

C12

RESETB

Input

Active Low Reset Input. RESETB places digital logic and

SPI registers in a known default state. RESETB must be

connected to a digital IC that is capable of issuing a reset

signal for the first step in the device initialization process.

E13, D13

RXEN0, RXEN1

Input

Active High ADC and Receive Datapath Enable Inputs.

RXENx is also SPI configurable.

P13, R13

TXEN0, TXEN1

Input

Active High DAC and Transmit Datapath Enable Inputs.

TXENx is also SPI configurable.

D12, D11

ADC0_FD0, ADC0_FD1

Output

ADC0 Fast Detect Outputs by Default. Do not connect if

unused.

E12, E11

ADC1_FD0, ADC1_FD1

Output

ADC1 Fast Detect Outputs by Default. Do not connect if

unused.

F12, F11

ADC2_FD0, ADC2_FD1

Output

ADC2 Fast Detect Outputs by Default. Do not connect if

unused.

G12, G11

ADC3_FD0, ADC3_FD1

Output

ADC3 Fast Detect Outputs by Default. Do not connect if

unused.

P12, R12

IRQB_0, IRQB_1

Output

Interrupt Request Outputs. These pins are open-drain, active

low outputs (CMOS levels with respect to DVDD1P8). Connect

a >5 kΩ pull-up resistor to DVDD1P8 to prevent these pins

from floating when unused.

N12, M12, N11, M11, P11, R11

GPIO0 to GPIO5

Input/output

General-Purpose Input or Output Pins. These pins control

auxiliary functions related to the Tx datapaths.

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